Timing control to generate signals

[Konx]

Hi everyone (again ).

I have another question for you, a bit more complicated than the
previous one, (I guess).

I have a module called logic_generator.v

This module has to produce some signals with a predetermined timing.
Example:

- When the signal "start" is high (start = 1) a cycle begin
- In this cycle, I want something like this: (unit is ns)


#10 reset = 1;
#10 reset = 0;

#10 hit = 1;
#(time_defined_by_user_1) hit = 0;

#(time_defined_by_user_2) token = 1;
#100 token = 0;

Question 1: how can I define these times in a way that they can be
synthesized? I'm reading a Verilog manual, and they say the above
writing is used only for testbenches, not for synthesizeable logic.
But what I need is that the FPGA (that is the target of the previous
code) produces the signal according to the user definition.

Question 2: how can I define with respect to the same t=0? I mean,
after reset goes to zero, I want to wait 10ns before the hit signal is
asserted (and this is ok) but then I want to wait an amount of time
equals to time_defined_by_user_2 before token is high, BUT this time
should be calculated with respect to the time that reset goes to zero,
not with respect to the hit goes to zero. (I hope the question is
clear...).

Can I do something like: #(10 + time_defined_by_user_1 -
time_defined_by_user_2)? because the main point is that (according to
the situation I want to obtain) the token could be asserted to high
BEFORE the hit signal arrives (or when the hit signal is still high).

All this stuff has to be loaded inside an FPGA that have to generate
the control logic for a chip, but if the time delay cannot be
synthesized, how can I do this?

Thanks for help ^^

Francesco.

 

[gabor]

On Feb 12, 8:43 am, Konx <cesco...@gmail.com> wrote:

Hi everyone (again ).

I have another question for you, a bit more complicated than the
previous one, (I guess).

I have a module called logic_generator.v

This module has to produce some signals with a predetermined timing.
Example:

- When the signal "start" is high (start = 1) a cycle begin
- In this cycle, I want something like this: (unit is ns)

#10 reset = 1;
#10 reset = 0;

#10 hit = 1;
#(time_defined_by_user_1) hit = 0;

#(time_defined_by_user_2) token = 1;
#100 token = 0;

Question 1: how can I define these times in a way that they can be
synthesized? I'm reading a Verilog manual, and they say the above
writing is used only for testbenches, not for synthesizeable logic.
But what I need is that the FPGA (that is the target of the previous
code) produces the signal according to the user definition.

Question 2: how can I define with respect to the same t=0? I mean,
after reset goes to zero, I want to wait 10ns before the hit signal is
asserted (and this is ok) but then I want to wait an amount of time
equals to time_defined_by_user_2 before token is high, BUT this time
should be calculated with respect to the time that reset goes to zero,
not with respect to the hit goes to zero. (I hope the question is
clear...).

Can I do something like: #(10 + time_defined_by_user_1 -
time_defined_by_user_2)? because the main point is that (according to
the situation I want to obtain) the token could be asserted to high
BEFORE the hit signal arrives (or when the hit signal is still high).

All this stuff has to be loaded inside an FPGA that have to generate
the control logic for a chip, but if the time delay cannot be
synthesized, how can I do this?

Thanks for help ^^

Francesco.

For a testbench you could have multiple processes to
run your different delays that need to start at the same
time.

e.g.

always @ (posedge reset_n) begin
#10 hit = 1;
end

always @ (posedge reset_n) begin
#(user_defined_time1) hit = 0;
end

For synthesis you need to have a clocked process. You'll need
a clock that runs fast enough to meet your needs for timing
resolution.

HTH,
Gabor

 

[David Rogoff]

On 2010-02-12 05:43:22 -0800, Konx said:

Question 1: how can I define these times in a way that they can be
synthesized? I'm reading a Verilog manual, and they say the above
writing is used only for testbenches, not for synthesizeable logic.
But what I need is that the FPGA (that is the target of the previous
code) produces the signal according to the user definition.

Nope. Think about it - what hardware would you expect the synthesis
tool to implement to do this? All it's got are gates and flip-flops.
You would need to make a timer with a counter. If you need delays
smaller than a clock period, you've got problems.