Timing Constraints: are there any "design patterns" indicati

[Tom Gardner]

I'll shortly be starting a design in a Zynq FPGA using Vivado. I'm confident
that I will be able to use VHDL to create the design, partly because it isn't
outside my comfort zone, and partly because there are many app notes/tutorials
/books etc on that subject. Timing constraints are a different issue, mainly
because they seem to be relatively neglected and un-glamorous.

What I would really like are some examples of "good practice", i.e. small
self-contained examples using timing constraints, documenting what is necessary
and what is sufficient, and why. I emphasise "small and self-contained" since
at this stage I'm not interested in all the arcane possibilities of the
constraint languages, merely the common cases with their boundaries. In the
software community such things have been given the somewhat fancy name of
"design patterns", but it is a valuable concept.

So, I'd be grateful for pointers to references that you found useful when you
were learning how to use constraints effectively.

Background is that the logic design will be conventional, with patterns based
around
* blocks containing FSMs in the form of one VHDL process for the
combinatorial logic plus another VHDL process for the registers
* two (or more!) clock domains, some with period X, some period 8X (i.e.
a nice simple integer relationship)
* re-synchronisation across those domain boundaries, using predefined
standard Xilinx FPGA primitives
* external i/o timing is, perhaps surprisingly, "don't care"; I'll
resynchronise inputs myself, and will accept whatever the outputs provide
* and I'm presuming that the PL<->PS interface will be "dealt with" by Vivado
without my intervention

So, I'd be grateful for pointers to references that you found useful when you
were learning how to use constraints effectively.

 

[kaz]

see altera timequest design centre

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Posted through http://www.FPGARelated.com

 

[Theo Markettos]

Tom Gardner <spamjunk@blueyonder.co.uk> wrote:

So, I'd be grateful for pointers to references that you found useful when you
were learning how to use constraints effectively.

I don't speak Xilinx, but in Altera land it should be enough to specify the
input clocks and let the tools figure out the rest: they know about PLLs and
clock crossing components.

Though you may have to constrain your external I/O if you get problems -
while the tools know what to do with existing interfaces (like memory PHYs),
you may have to put in rules to say 'don't care' to wires you expose from
your own VHDL, otherwise they may try harder to constrain things you don't
want - or underconstain them if there is an innate timing relationship (eg
something like SPI where the ordering of clock and data edges matters
somewhat)

Theo