timing constraints and enables

[Ken]

Hello again,

CLK = 280MHz

A state machine clocked by CLK and enabled by NSI generates a CLKEN signal
that enables "other" logic clocked by CLK.

CLK and NSI are on the entity, CLKEN is internal.

The "other" logic contains long carry chains that will run at 140MHz (just).

The FSM should be able to run at ~280MHz on a virtex-ii -5.

I am assuming NSI always = 1 for the time being.

How do I describe this situation to Xilinx ISE 5.2.03i in ucf constraints
please?

I tried this:

NET "CLK*" TNM_NET = "CLK";
NET "CLKEN" TNM_NET = "CLKEN";
NET "NSI*" TNM_NET = "NSI";

TIMESPEC "TS_CLK" = PERIOD "CLK" 3.57 ns HIGH 50 %;
TIMESPEC "TS_CLK_NSI" = FROM "CLK" TO "NSI" "TS_CLK" * 1;
TIMESPEC "TS_CLK_CLKEN" = FROM "CLK" TO "CLKEN" "TS_CLK" * 2;


but ISE tries to constrain the "other" logic with the carry chains to the
280MHz clock instead of the 140MHz CLKEN domain - and timing fails.

Also tried various other combinations some of which are listed at the end
with no success.

Am I on the right lines here or am I missing something obvious? Surely I
can tell ISE about this situation...?

Also, is there any way to use say "CLKEN*" when specifying the grouping for
CLKEN - do I need to dig in to the hierarchy somehow? Tried the Xilinx
manuals but couldn't find something that relates to this scenario without
specifying every signal manully - I need to group by enable/clk signal!

Thanks for your time,

Ken


#TIMESPEC "TS_CLKEN" = FROM "CLKEN" TO "CLKEN" "TS_CLK" * 2;
#TIMESPEC "TS_CLKEN_CLK" = FROM "CLKEN" TO "CLK" "TS_CLK" * 2;
#TIMESPEC "TS_NSI" = FROM "NSI" TO "NSI" "TS_CLK" * 2;
#TIMESPEC "TS_NSI_CLK" = FROM "NSI" TO "CLK" "TS_CLK" * 2;


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[Ken]

(snip)

I tried this:

NET "CLK*" TNM_NET = "CLK";
NET "CLKEN" TNM_NET = "CLKEN";
NET "NSI*" TNM_NET = "NSI";

TIMESPEC "TS_CLK" = PERIOD "CLK" 3.57 ns HIGH 50 %;
TIMESPEC "TS_CLK_NSI" = FROM "CLK" TO "NSI" "TS_CLK" * 1;
TIMESPEC "TS_CLK_CLKEN" = FROM "CLK" TO "CLKEN" "TS_CLK" * 2;


but ISE tries to constrain the "other" logic with the carry chains to the
280MHz clock instead of the 140MHz CLKEN domain - and timing fails.

I can now answer my own question...

Problem is that ISE 5.2.03i will not recognise "CLKEN*" but WILL recognise
"clken*" and correctly analyse the paths that use the internally generated
clken.

Seems ISE has a problem with case mismatches for signals specified in ucf
using wildcards....ISE manages case insensitive matches for signals without
wildcards though.

Cheers,

Ken