timing constraints... again

M

Marija

Guest
Hi all, <p>no metter how hard I try, I <BR>
couldn't find an appropriate way <BR>
to set timing constraints to my <BR>
project. The thing is, I <BR>
create .xcf file, add it to the <BR>
project, run synthesis, run <BR>
translate, map and par and the <BR>
effect is that all of my timing <BR>
constraints are met. When I run <BR>
the Timing Analysis, the reported <BR>
clk period is even shorter than <BR>
the one I need. Ok, I run <BR>
simulation using ModelSim and .sdf <BR>
and .vhd files which ISE PAR <BR>
generated - and get simulation <BR>
errors caused by too short clk <BR>
period! How can I be sure that the <BR>
tool 'understood' my constraints <BR>
and implemented them as well? <p>Thanks in advance! <p>Marija
 
Hi Christian, <p>I did change the reesolution to a <BR>
ps, but the timing constraints is <BR>
in ns, anyway. Still, it doesn't <BR>
work :( <p>Marija
 
Hi Marija,

maybe you didn't change your simulation resolution
to ps? (it is the -t option, or can also be found
in a pull down menu in the ModelSim GUI)

Christian
 
Christian Haase &lt;nospams@today.de&gt; wrote in message news:&lt;4073cb1f$1@news.fhg.de&gt;...
Hi Marija,

maybe you didn't change your simulation resolution
to ps? (it is the -t option, or can also be found
in a pull down menu in the ModelSim GUI)

Christian
Click to expand...
Another possibility is that your constraints are
not actually constraining the signals you think
they are. For PERIOD constraints make sure that
you place the constraint after the DCM (pin period
constraints don't always propagate through DCM
or DLL). A good thing to check is the place and
route report, which has a clock report and a constraint
report at the end. Make sure your PERIOD constraints
cover all listed clocks. Look at the constraint
report for "N/A" entries which may indicate constraints
that cover no paths.
 
there are two possibility one u may not have apply reset for long enough time ,which will not initialise internal logic properly(this will be case if u r using asyncronous reset) <p>nother possibility is if ur toplevel entity has bidirectional port then dont forget to use pullup/pulldown resistor model in test bench <p>let me know is this help u or not
 
hi Marija <p>there are two possibility one u may not have apply reset for long enough time ,which will not initialise internal logic properly(this will be case if u r using asyncronous reset) <p>nother possibility is if ur toplevel entity has bidirectional port then dont forget to use pullup/pulldown resistor model in test bench <p>let me know is this help u or not
 
On Thu, 8 Apr 2004 06:52:13 -0700, khamkar77 &lt;khamkar77@yahoo.co.in&gt;
wrote:


Click to expand...
Kindly post in plain text in future.
--
Jonathan Bromley, Consultant

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