timescale

[mjl296@hotmail.com]

This is a style question that has bugged me for ages...

In RTL I do not use # delays, therefore I do not put in a `timescale
directive.
In the testbench I do use # delays, therefore I do put in a `timescale
directive.
The simulator complains that `timescale has been specified for some,
but not all modules.

What do others do to deal with the simulator warnings.

 

[gabor]

On Sep 18, 5:22 am, "mjl...@hotmail.com" <mjl...@hotmail.com> wrote:

This is a style question that has bugged me for ages...

In RTL I do not use # delays, therefore I do not put in a `timescale
directive.
In the testbench I do use # delays, therefore I do put in a `timescale
directive.
The simulator complains that `timescale has been specified for some,
but not all modules.

What do others do to deal with the simulator warnings.

I generally add a timescale directive to all of my files.
Consider it part of the file header along with the comments
for author, date, and copyright. If you don't use # delays
for RTL (I assume you mean for synthesis), the timescale is
ignored. This also keeps you out of trouble if the default
timescale for ModelSim (or whatever you use) changes.

I also have learned to ignore warnings. It is unreasonable
to assume that a design will synthesize and simulate without
any warnings at all. So I just get used to which warnings I
can safely ignore and get on with the important issues of design.

Just my 2 cents,
Gabor

 

I create a 1-line file timescale.v which contains the timescale.
This should be the first file compiled by the simulator.
Then you don't have to worry about the simulators default timescale.

Just my approach.
Uday

 

[lipmin.khor@gmail.com]

On Sep 18, 10:22 am, "mjl...@hotmail.com" <mjl...@hotmail.com> wrote:

This is a style question that has bugged me for ages...

In RTL I do not use # delays, therefore I do not put in a `timescale
directive.
In the testbench I do use # delays, therefore I do put in a `timescale
directive.
The simulator complains that `timescale has been specified for some,
but not all modules.

What do others do to deal with the simulator warnings.

I would use the -timescale option for the simulator, this will
implicitly add timescale to files that do not have it defined. If you
have different timescale values on your files, you might want to try -
override_timescale but I dont recommend this as it will mess up your
PLL/memory models which require specific timescale.

Good luck
LipMin