N
Neo
Guest
Hi,
I am plagued by lot of timescale mismatches in RTL files which are
many and I preferably don't want to modify. Is there any directive
which I can give to ncsim for overriding the timescale directive for
the simulation. I don't think there is but does verilog 2001 or later
provide any help in this regard?
Thanks,
Neo
I am plagued by lot of timescale mismatches in RTL files which are
many and I preferably don't want to modify. Is there any directive
which I can give to ncsim for overriding the timescale directive for
the simulation. I don't think there is but does verilog 2001 or later
provide any help in this regard?
Thanks,
Neo