timescale in VHDL

Hi,
Like in verilog we do have `timescale directive for specifying
reference time unit for simulator, do we have something like that in
VHDL?? if yes do tell the syntax?

Shantanu

 

[Kim Enkovaara]

shantanu_gupta2kplus2@yahoo.co.in wrote:

Like in verilog we do have `timescale directive for specifying
reference time unit for simulator, do we have something like that in
VHDL?? if yes do tell the syntax?

There is no timescale directive in VHDL. VHDL has native type "time" which
can be used. At least in 1076-1993 standard it has units (fs,ps,ns,us,ms,sec,
min,hr). The simulator resolution is usually set from command line or trough
configuration files. So in VHDL you can say

WAIT FOR 510.1ns;
sig1 <= TRANSPORT '1' AFTER 120ps;

--Kim

 

[Mike Treseler]

shantanu_gupta2kplus2@yahoo.co.in wrote:

Like in verilog we do have `timescale directive for specifying
reference time unit for simulator, do we have something like that in
VHDL??

VHDL uses time units, 5 ns, 10 uS etc.
Resolution is a simulator setting.

-- Mike Treseler

 

[Allan Herriman]

On 23 Feb 2006 05:04:09 -0800, shantanu_gupta2kplus2@yahoo.co.in
wrote:

Hi,
Like in verilog we do have `timescale directive for specifying
reference time unit for simulator, do we have something like that in
VHDL?? if yes do tell the syntax?

In addition to what the other posters said, you should be vary careful
when setting the simulator resolution. If this resolution is more
coarse that the resolution implied by the time values in the source
code, the time values will not be simulated correctly.

e.g.

sig1 <= val1 after 1.234 ns

The implied resolution there is 0.001 ns, or 1 ps.

If the simulator is set to (say) 100 ps resolution, the delay will be
truncated to 1.2 ns.
The simulator will typically issue a warning if this happens.

Regards,
Allan