timescale and duty cycle

Hi Group,

I'm new to verilog. How can I specify timescale for a code which its
clock period is 100 ns and a duty cycle of 25% it considerd for it?

Can somebody help me to understand duty cycle?

Thanks,

 

ramsin.savra@gmail.com wrote:

Hi Group,

I'm new to verilog. How can I specify timescale for a code which its
clock period is 100 ns and a duty cycle of 25% it considerd for it?

Can somebody help me to understand duty cycle?

Thanks,

First of all, timescale is used for simulation only. It has two
parts. The first indicates the time value of one "time unit" in the
simulation. So when you put those #1, #2, etc. into the source code
this is the time unit multiplied by the 1 (2, etc.) to generate the
delay.

The second part indicates the resolution of the simulation. This
indicates
the minimum step size from one event to another. So in your case the
clock could be modeled with a simulation step as large as 25nS, however
if you want the simulation to show reasonable times for gate delays
you would generally make it much smaller (100pS or less).

Duty cycle in a clock is just high vs. low time. For your clock with
a timescale of 1nS / xxxpS (1nS is the time unit) you could write:

initial begin
clock = 0;
. . . // other initializations
end

always begin
clock = #75 1;
clock = #25 0;
end

Then your clock would be high for 25 nS and low for 75 nS (starting
in the low state in this instance.