timer program

Guest
Hi all,

I have another issue. The following code, when programmed to my
spartan 3 board, doesn't function correctly. I am trying to input a
50Khz signal in my design and output left and right pulses, at 25% -
75% of the 50Khz signal. So, at the high phase, 25% - 75% of the way,
I output a left signal, and then, at 25% -75% at the low phase of the
50Khz signal.

Thanks,
 
On Oct 31, 4:28 pm, uraniumore...@gmail.com wrote:
Hi all,

I have another issue. The following code, when programmed to my
spartan 3 board, doesn't function correctly. I am trying to input a
50Khz signal in my design and output left and right pulses, at 25% -
75% of the 50Khz signal. So, at the high phase, 25% - 75% of the way,
I output a left signal, and then, at 25% -75% at the low phase of the
50Khz signal.

Thanks,
Click to expand...
module Timer(clk_50Mhz, pem_50Khz,left , right, reset, button1, high,
low);
input clk_50Mhz;
input pem_50Khz;
input reset;
output reg left ;
output reg right;
reg [14:0] count;
input button1;
output reg high;
output reg low;

always @ (posedge pem_50Khz or negedge pem_50Khz)
begin
if(pem_50Khz)
begin high = 1;
low = 0;
end
else if (~pem_50Khz)
begin high = 0;
low = 1;
end
end
always @ (posedge clk_50Mhz)
begin

if(reset)
begin
count = 0;
left = 0;
right = 0;
end

else if (high && button1)
begin
if(count == 125)
left = 1;
else if(count == 375)
left = 0;
count = count + 1;
end
else if (low && button1)
begin
if (count == 125)
right = 1;
else if (count == 375)
right = 0;
count=count+1;
end


if (count == 500)
count = 0;
end

endmodule
 
On Oct 31, 10:55 pm, uraniumore...@gmail.com wrote:
On Oct 31, 4:28 pm, uraniumore...@gmail.com wrote:

Hi all,

I have another issue. The following code, when programmed to my
spartan 3 board, doesn't function correctly. I am trying to input a
50Khz signal in my design and output left and right pulses, at 25% -
75% of the 50Khz signal. So, at the high phase, 25% - 75% of the way,
I output a left signal, and then, at 25% -75% at the low phase of the
50Khz signal.

Thanks,

module Timer(clk_50Mhz, pem_50Khz,left , right, reset, button1, high,
low);
input clk_50Mhz;
input pem_50Khz;
input reset;
output reg left ;
output reg right;
reg [14:0] count;
input button1;
output reg high;
output reg low;

always @ (posedge pem_50Khz or negedge pem_50Khz)
begin
if(pem_50Khz)
begin high = 1;
low = 0;
end
else if (~pem_50Khz)
begin high = 0;
low = 1;
end
end
always @ (posedge clk_50Mhz)
begin

if(reset)
begin
count = 0;
left = 0;
right = 0;
end

else if (high && button1)
begin
if(count == 125)
left = 1;
else if(count == 375)
left = 0;
count = count + 1;
end
else if (low && button1)
begin
if (count == 125)
right = 1;
else if (count == 375)
right = 0;
count=count+1;
end

if (count == 500)
count = 0;
end

endmodule
Click to expand...
Any suggestions ???
 
<uraniumore238@gmail.com> wrote in message
news:eb779f62-4d82-491a-8ac3-96244cbba865@b2g2000prf.googlegroups.com...
On Oct 31, 10:55 pm, uraniumore...@gmail.com wrote:
On Oct 31, 4:28 pm, uraniumore...@gmail.com wrote:

Hi all,

I have another issue. The following code, when programmed to my
spartan 3 board, doesn't function correctly. I am trying to input a
50Khz signal in my design and output left and right pulses, at 25% -
75% of the 50Khz signal. So, at the high phase, 25% - 75% of the way,
I output a left signal, and then, at 25% -75% at the low phase of the
50Khz signal.

Thanks,

module Timer(clk_50Mhz, pem_50Khz,left , right, reset, button1, high,
low);
input clk_50Mhz;
input pem_50Khz;
input reset;
output reg left ;
output reg right;
reg [14:0] count;
input button1;
output reg high;
output reg low;

always @ (posedge pem_50Khz or negedge pem_50Khz)
begin
if(pem_50Khz)
begin high = 1;
low = 0;
end
else if (~pem_50Khz)
begin high = 0;
low = 1;
end
end
always @ (posedge clk_50Mhz)
begin

if(reset)
begin
count = 0;
left = 0;
right = 0;
end

else if (high && button1)
begin
if(count == 125)
left = 1;
else if(count == 375)
left = 0;
count = count + 1;
end
else if (low && button1)
begin
if (count == 125)
right = 1;
else if (count == 375)
right = 0;
count=count+1;
end

if (count == 500)
count = 0;
end

endmodule

Any suggestions ???
..
Click to expand...
Wait at least 24 hours for more of the world to see your message
before deciding you aren't going to get a reply.

Also, include more detail on what type of possible problem you
want people to look for.
 
On Oct 31, 10:55 pm, uraniumore...@gmail.com wrote:
On Oct 31, 4:28 pm, uraniumore...@gmail.com wrote:

Hi all,

I have another issue. The following code, when programmed to my
spartan 3 board, doesn't function correctly.
Click to expand...
<snip>

        always @ (posedge pem_50Khz or negedge pem_50Khz)
Click to expand...
<snip>

Are you saying you got this to compile properly to a Spartan-3
project? The posedge/negedge should have thrown up synthesis
problems. Please tell us what you *did* get.
 
On Nov 1, 7:41 am, John_H <newsgr...@johnhandwork.com> wrote:
On Oct 31, 10:55 pm, uraniumore...@gmail.com wrote:

On Oct 31, 4:28 pm, uraniumore...@gmail.com wrote:

Hi all,

I have another issue. The following code, when programmed to my
spartan 3 board, doesn't function correctly.

snip

always @ (posedge pem_50Khz or negedge pem_50Khz)

snip

Are you saying you got this to compile properly to a Spartan-3
project? The posedge/negedge should have thrown up synthesis
problems. Please tell us what you *did* get.
Click to expand...
Okay, this is my new timer program. Is there any issues that you can
see ?

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:53:14 10/25/2008
// Design Name:
// Module Name: Timer
// Project Name:
// Target Devices:
// Tool versions:
// Description: This module accepts input from the pem device running
at 50Khz and
// asserts the left signal and then asserts the right signal
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Timer(clk_50Mhz, pem_50Khz,left , right, reset, button1, high,
low);
input clk_50Mhz;
input pem_50Khz;
input reset;
output reg left ;
output reg right;
reg [14:0] countr;
reg [14:0] countl;
input button1;
output reg high;
output reg low;

always @ (posedge clk_50Mhz)
begin

if(reset)
begin
countl = 0;
left = 0;
end
else if (pem_50Khz && button1)
begin
if(countl == 125)
left = 1;
else if(countl == 375)
left = 0;
countl = countl + 1;
end

if (countl == 500 || ~button1)
begin
countl = 0;
left = 0;
end

end

always @ (negedge clk_50Mhz)
begin
if(reset)
begin
countr = 0;
right = 0;
end

else if (~pem_50Khz && button1)
begin
if (countr == 125)
right = 1;
else if (countr == 375)
right = 0;
countr=countr+1;
end

if (countr == 500 || ~button1)
begin
countr = 0;
right = 0;
end
end
endmodule
 
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