Time slot in Verilog?

S

Shenli

Guest
Hi all,

When reading Verilog article, I am confused with time slot idea.

For example, a non-blocking assignment,
@(posedge clk) DOUT<= #1 DIN;

Will this assignment completed in one time slot or two time slots
(Evaluate RHS at 1st time slot; and update LHS of NBA at 2st time
slot)?

BTW, is there any article visualize the #delay in Verilog time slot?
Thanks!

Best regards,
Davy
 
On Dec 6, 8:18 pm, "Shenli" <zhushe...@gmail.com> wrote:
Hi all,

When reading Verilog article, I am confused with time slot idea.

For example, a non-blocking assignment,
@(posedge clk) DOUT<= #1 DIN;

Will this assignment completed in one time slot or two time slots
(Evaluate RHS at 1st time slot; and update LHS of NBA at 2st time
slot)?

BTW, is there any article visualize the #delay in Verilog time slot?
Thanks!

Best regards,
Davy
Click to expand...

take an example your

at 3th unit DIN = 16'd10;
at 4th unit DOUT = 16'd10.

Here may be you are referring 1st time slot as the 3rd unit and 2nd
time slot as 4th.

http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf
read this for more info
 
what i meant was

suppose ur DIN is changing at time X..
your clock is changing at time X+1,
DOUT is supposed to change at X+1 as DIN is already set by that time ,
due to #1 you will see the change of DOUT at X+2.
 
Hi terabits,

Thanks a lot for the paper link!

Best regards,
Shenli

terabits wrote:
On Dec 6, 8:18 pm, "Shenli" <zhushe...@gmail.com> wrote:
Hi all,

When reading Verilog article, I am confused with time slot idea.

For example, a non-blocking assignment,
@(posedge clk) DOUT<= #1 DIN;

Will this assignment completed in one time slot or two time slots
(Evaluate RHS at 1st time slot; and update LHS of NBA at 2st time
slot)?

BTW, is there any article visualize the #delay in Verilog time slot?
Thanks!

Best regards,
Davy


take an example your

at 3th unit DIN = 16'd10;
at 4th unit DOUT = 16'd10.

Here may be you are referring 1st time slot as the 3rd unit and 2nd
time slot as 4th.

http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf
read this for more info
Click to expand...
 
I have got a response from a Guru.

My question:
But how about the traditional NBA in module (not program) like
"@(posedge clk) DOUT<= #1 DIN;", the simulator will follow what order
to spawn NBA in module with delay to another time slot?
Click to expand...
His answer:
On a posedge clk, DIN will be sampled and then scheduled for update in
the NBA region of the time slot that occurs #1 after the posedge clk.

This is how these events are scheduled with Verilog-2001

Thanks,
Shenli

Shenli wrote:
Hi terabits,

Thanks a lot for the paper link!

Best regards,
Shenli

terabits wrote:
On Dec 6, 8:18 pm, "Shenli" <zhushe...@gmail.com> wrote:
Hi all,

When reading Verilog article, I am confused with time slot idea.

For example, a non-blocking assignment,
@(posedge clk) DOUT<= #1 DIN;

Will this assignment completed in one time slot or two time slots
(Evaluate RHS at 1st time slot; and update LHS of NBA at 2st time
slot)?

BTW, is there any article visualize the #delay in Verilog time slot?
Thanks!

Best regards,
Davy


take an example your

at 3th unit DIN = 16'd10;
at 4th unit DOUT = 16'd10.

Here may be you are referring 1st time slot as the 3rd unit and 2nd
time slot as 4th.

http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf
read this for more info
Click to expand...
 
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