TIME borrowing in synthesis

[whizkid]

I am seeing messages like



Time Borrowing Information
--------------------------------------------------------------
CLK pulse width 0.75
library setup time -0.11
--------------------------------------------------------------
max time borrow 0.64
actual time borrow 0.50
--------------------------------------------------------------


in Design Compiler log file...

can anyone tell me what is this time borrowing ..

thanks
whizkid

 

[Tom Verbeure]

Time borrowing is a concept that is used in latch based pipelines in
which you typically have 2 stages of combinatorial surrounded by
latches. If the first combinational piece of logic has a much longer
delay than the second one, you can borrow some of the time of the
second part to the first part. A somewhat more comprehensive
explanatation can be found here:

http://www.synopsys.com/products/logic/design_comp_tb.html

Search for 'borrowing'...
We have used this technique in FF based design where we captured the
output of a RAM that was too slow to finished in a clock cycle and then
registered it with FF's in a later stage. The use of latches in
standard FF based design kills regular scan-based testing, so these
technique should be used with great care!

Since these latches aren't used a lot these day, my guess is that you
unintentionally added latches to your design and this resulted in the
warning above. If this is the case, just remove them and the warning
will be gone.

Tom