Threshold Voltage Confirmation

S

sykab

Guest
Hi again!

To know if a MOS is in the saturation region, vds should be more or
equal to (vgs-VT).
I'm using cmos 0,35 um AMS technology. I'm supposing that VT is equal
to 0,8 V.
Am I doing it right?

Thanks
 
Hi There !

The Last time I worked with this AMS 0.35u process was when at the
uni ... ages ago !
So I don't really know what's the VT value on this PDK but I can give
you a hint to get it yourself without asking anybody but your best
ever companion for this kind of requests : Spectre !

1. A MOS is operating in saturation mode when both of the following
conditions are satisfied :
Cond_1: VGS > VTH
Cond_2: VDS > (VGS-VTH)

That's of course for N-type Fets, just reverse it for the P ones.

2. To get your VTH from Spectre, just run a DC OP on your schematic
and the go to :
Analog Design Environment Window -> Results -> Print -> DC Operating
Point
This menu should be active (not grayed) if you've already done a DC
(with saving OP points) simulation.

So when you hit this 'DC operating Points' menu, Cadence comes with a
blank window called 'Results Display Window'.
This window is empty so far because it's waiting for you to select the
device from the schematic.
If you give a look at the bottom left corner of your current schematic
window, you should see the following message :
Ready> select instances for the MP output ...
You know then what you do ! Just hit that device and you get your
Rsults display window nicely decorated !

You will find there all the outputs you need for your transistor,
including the VTH

This is the simplest way for you to get the VTH

There are other ways to print this value if don't like the GUIs but I
don't recommend it for you.

BTW, among this huge list of output parameters, there is one that
could interests you : "region"
I'm not gonna tell you what it is, just search in the Spectre
documentation and you will understand why I'm talking about it ...

Enjoy yourself !

Riad.
 
On 2 Maio, 19:07, Riad KACED <riad.ka...@gmail.com> wrote:
Hi There !

The Last time I worked with this AMS 0.35u process was when at the
uni ... ages ago !
So I don't really know what's the VT value on this PDK but I can give
you a hint to get it yourself without asking anybody but your best
ever companion for this kind of requests : Spectre !

1. A MOS is operating in saturation mode when both of the following
conditions are satisfied :
Cond_1: VGS > VTH
Cond_2: VDS > (VGS-VTH)

That's of course for N-type Fets, just reverse it for the P ones.

2. To get your VTH from Spectre, just run a DC OP on your schematic
and the go to :
Analog Design Environment Window -> Results -> Print -> DC Operating
Point
This menu should be active (not grayed) if you've already done a DC
(with saving OP points) simulation.

So when you hit this 'DC operating Points' menu, Cadence comes with a
blank window called 'Results Display Window'.
This window is empty so far because it's waiting for you to select the
device from the schematic.
If you give a look at the bottom left corner of your current schematic
window, you should see the following message :
Ready> select instances for the MP output ...
You know then what you do ! Just hit that device and you get your
Rsults display window nicely decorated !

You will find there all the outputs you need for your transistor,
including the VTH

This is the simplest way for you to get the VTH

There are other ways to print this value if don't like the GUIs but I
don't recommend it for you.

BTW, among this huge list of output parameters, there is one that
could interests you : "region"
I'm not gonna tell you what it is, just search in the Spectre
documentation and you will understand why I'm talking about it ...

Enjoy yourself !

Riad.
Click to expand...
Hi!
I knew the Results Display Window. And I've already done what you
said.
The problem is when I want to dimension a MOS with a current and vgs
defined. If it's in the saturation region, I'll just need the
threshold voltage.
Furthermore, when I look to the vth in the results I see that it isn't
constant because it depends on a lot of things.
I thing that I have to study tthe Spectre Documentation, as you advice
me.

Thanks again

Sara
 
Ohh Yes I see !

Is the bulk of your MOS tied to the Source ?
If not, your VTH will be strongly impacted by the Body Effect.

Remember that the VTH equation is roughly given by :

Vth = Vth0 + Gamma*{sqrt(abs(Vsb-2*PhiFs))-sqrt(abs(2*PhiFs))} with :
Vth0 is the Th volltage at Vsb=0 (i,e Vsource tied to Vbulk)
Gamma = The body effect factor
Vsb = Source to Bulk voltage
PhiFS = The Fermi Level stuff ... (never remember the name)

So if Vsb = 0, then Vth = Vth0 otherwise Vth will be greater.

You may to take this into account.

This is a weak point of the NMOS compared to the P-one. Since the Pmos
is drawn in an N-well, you can always tie the S-B nodes. But the NMOS
is in the global substrate ...
This could be solved if you process offers Deep-Nwells that can help
in creating isolated Pwells.

Other parameters like Well Proximity Effects (WPE), Shallow Trench
Isolation (STI) Stress ... impact the value of the VTh but it is a
third order impact ...

Look at your MOs model documentation (MM9, BSIM3, BSIM4 ...) for more
details.

i don't know what you're designing but in a case of diff pair for
example, the current is fixed by the current source/mirror, the Diff-
pair transistors will then adjust their VGS to match the current fixed
by the source. The value of the VGS id of course dependent of your W/L
ratio.

Good luck anyway !

Riad.
 
On 2 Maio, 21:30, Riad KACED <riad.ka...@gmail.com> wrote:
Ohh Yes I see !

Is the bulk of your MOS tied to the Source ?
If not, your VTH will be strongly impacted by the Body Effect.

Remember that the VTH equation is roughly given by :

Vth = Vth0 + Gamma*{sqrt(abs(Vsb-2*PhiFs))-sqrt(abs(2*PhiFs))} with :
Vth0 is the Th volltage at Vsb=0 (i,e Vsource tied to Vbulk)
Gamma = The body effect factor
Vsb = Source to Bulk voltage
PhiFS = The Fermi Level stuff ... (never remember the name)

So if Vsb = 0, then Vth = Vth0 otherwise Vth will be greater.

You may to take this into account.

This is a weak point of the NMOS compared to the P-one. Since the Pmos
is drawn in an N-well, you can always tie the S-B nodes. But the NMOS
is in the global substrate ...
This could be solved if you process offers Deep-Nwells that can help
in creating isolated Pwells.

Other parameters like Well Proximity Effects (WPE), Shallow Trench
Isolation (STI) Stress ... impact the value of the VTh but it is a
third order impact ...

Look at your MOs model documentation (MM9, BSIM3, BSIM4 ...) for more
details.

i don't know what you're designing but in a case of diff pair for
example, the current is fixed by the current source/mirror, the Diff-
pair transistors will then adjust their VGS to match the current fixed
by the source. The value of the VGS id of course dependent of your W/L
ratio.

Good luck anyway !

Riad.
Click to expand...
LOL!
That's what I'm doing, an opamp with a differential pair (to make part
of a current reference).
I tied the bulk of all nMOS to ground and the bulk of all pMOS to VCC.

Thanks
 
On May 3, 7:16 am, sykab <sara.cata...@gmail.com> wrote:
On 2 Maio, 21:30, Riad KACED <riad.ka...@gmail.com> wrote:



Ohh Yes I see !

Is the bulk of your MOS tied to the Source ?
If not, your VTH will be strongly impacted by the Body Effect.

Remember that the VTH equation is roughly given by :

Vth = Vth0 + Gamma*{sqrt(abs(Vsb-2*PhiFs))-sqrt(abs(2*PhiFs))} with :
Vth0 is the Th volltage at Vsb=0 (i,e Vsource tied to Vbulk)
Gamma = The body effect factor
Vsb = Source to Bulk voltage
PhiFS = The Fermi Level stuff ... (never remember the name)

So if Vsb = 0, then Vth = Vth0 otherwise Vth will be greater.

You may to take this into account.

This is a weak point of the NMOS compared to the P-one. Since the Pmos
is drawn in an N-well, you can always tie the S-B nodes. But the NMOS
is in the global substrate ...
This could be solved if you process offers Deep-Nwells that can help
in creating isolated Pwells.

Other parameters like Well Proximity Effects (WPE), Shallow Trench
Isolation (STI) Stress ... impact the value of the VTh but it is a
third order impact ...

Look at your MOs model documentation (MM9, BSIM3, BSIM4 ...) for more
details.

i don't know what you're designing but in a case of diff pair for
example, the current is fixed by the current source/mirror, the Diff-
pair transistors will then adjust their VGS to match the current fixed
by the source. The value of the VGS id of course dependent of your W/L
ratio.

Good luck anyway !

Riad.

LOL!
That's what I'm doing, an opamp with a differential pair (to make part
of a current reference).
I tied the bulk of all nMOS to ground and the bulk of all pMOS to VCC.

Thanks
Click to expand...

Don't know what's your transistor model. In common, BISM model is
always used and you could download the model document to check the
algorithm how to calculate the Vth and Vdsat.
 
Opamps ?! That's brilliant !

I wanted to adjust my last comments a little bit, just to make it more
accurate and thus less confusing for other folks.
I was talking about the STI and WPE just to give an example of what
could impact your Vth but these new silicon manufacturing side-effects
raise on small technology nodes only.
Depending on the foundry, the STI usually comes with 0.25um nodes and
beyond and WPE with ~ 90nm, 65nm and beyond (even I saw papers on
0.13um, the little gain does not worth the efforts spend on the
design, that's my point of view). In addition, WPE is supported with
BSIM4/PSP but not BSIM3.

Your AMS 0.35um is "too big" for this kind of effects ! I don't know
this process and I'm wondering if AMS is still using LOCOS isolation
instead of STI ?!!! never mind ! This data is just for your personal
knowledge ...

Hey Mobil !
Have you seen these equations yourself, give a quick a look at the
Appendix B of the BSIM3 pdf ... The Vth calculation stands on 2 pages
of very complicated mathematical which are not intended for a human
being reading but rather for simulators codings. The equation I
supplied above is good enough for a hand-made computation, let your
simulator does the complicated ones ... But If your are keen in
sinking your head into this, I can just say : GOOD LUCK ;-) ... I'm
too lazy for this, It's tiring me just in reading it !

Cheers,

Riad.
 
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