the textio lib and std_logic_textio

[Pedro Claro]

Greetings,

Recently I tried to use the facilities that textio has for my project.
I'm using Xilinx ISE 5.1 and strangely it appears that it complaints about
the std_logic_textio. It says that it doesn't exist in library IEEE.
I checked and the package is there. Of course I wrote in the top of my
project, "use ieee.std_logic_textio.all". I thought "hhhmm, maybe Xilinx
doesn't like the std_logic_textio, let's try the basic one: std.textio."
This one Xilinx recognizes but then it gives me errors saying that it doesn't
recognize the commands: LINE, TEXT, etc... It feels like Xilinx knows that
the package is there but doesn't use it.

Btw, I tried to copy-paste the textio package in my own package but then
it says that FILE is unsupported, and that ACCESS is unssoported.

Any ideias how to solve this?

Pedro Claro

 

[FE]

It's for simulation only. Not synthesisable.

regards
FE


"Pedro Claro" <orgulhosamenteso@hotmail.com> wrote in message
news:25c2602a.0307240824.1e15d4e7@posting.google.com...

Greetings,

Recently I tried to use the facilities that textio has for my project.
I'm using Xilinx ISE 5.1 and strangely it appears that it complaints about
the std_logic_textio. It says that it doesn't exist in library IEEE.
I checked and the package is there. Of course I wrote in the top of my
project, "use ieee.std_logic_textio.all". I thought "hhhmm, maybe Xilinx
doesn't like the std_logic_textio, let's try the basic one: std.textio."
This one Xilinx recognizes but then it gives me errors saying that it
doesn't
recognize the commands: LINE, TEXT, etc... It feels like Xilinx knows that
the package is there but doesn't use it.

Btw, I tried to copy-paste the textio package in my own package but then
it says that FILE is unsupported, and that ACCESS is unssoported.

Any ideias how to solve this?

Pedro Claro

 

[Pedro Claro]

Sorry about that double post.

I managed to search through the comp.lang.vhdl and found the answer for
my problem. I used the --pragma translate_off and on.
Well, as newbie in opening and writing files i have some questions.
Lets look at my example:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- pragma translate_off
use std.textio.ALL;
use ieee.std_logic_textio.all;

entity file_io is -- test bench
Port ( clock: in std_logic;
dout: out bit_vector(7 downto 0));

end file_io;

architecture test of file_io is

begin


read_file:
process(clock)
file my_input : TEXT open READ_MODE is "dados.cmd";
variable my_line : LINE;
variable my_input_line : LINE;
variable data: bit_vector(7 downto 0);
begin
if(rising_edge(clock)) then
write(my_line, string'("reading file"));
writeline(output, my_line);
readline(my_input, my_input_line);
read(my_input_line,data);
writeline(output, my_input_line);

read(my_input_line,data);
write(my_line,string'("Data contains:"));
writeline(output,my_line);
write(my_line, data);
writeline(output,my_line);
-- is this possible??
-- dout <= data;

end if;
end process read_file;

end architecture test; -- of file_io

--prama translate_on

Well, this code gives me the following error:

TEXTIO procedure READ (BIT_VECTOR) : Parameter L of type LINE is empty.

And this is the contents of my file:

00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
10000000
01000000
00100000
00010000
11111111


I've tried also the hread form the ieee.std_textio but it was a mess.
( of course with a hexadecimal data file, AAA, 0000 , etc.. )
Can anyone give me a tip here? Like somesort of template for reading files
and putting the values on some outports?


orgulhosamenteso@hotmail.com (Pedro Claro) wrote in message news:<25c2602a.0307240824.1e15d4e7@posting.google.com>...

Greetings,

Recently I tried to use the facilities that textio has for my project.
I'm using Xilinx ISE 5.1 and strangely it appears that it complaints about
the std_logic_textio. It says that it doesn't exist in library IEEE.
I checked and the package is there. Of course I wrote in the top of my
project, "use ieee.std_logic_textio.all". I thought "hhhmm, maybe Xilinx
doesn't like the std_logic_textio, let's try the basic one: std.textio."
This one Xilinx recognizes but then it gives me errors saying that it doesn't
recognize the commands: LINE, TEXT, etc... It feels like Xilinx knows that
the package is there but doesn't use it.

Btw, I tried to copy-paste the textio package in my own package but then
it says that FILE is unsupported, and that ACCESS is unssoported.

Any ideias how to solve this?

Pedro Claro

 

[Mike Treseler]

Pedro Claro wrote:

I've tried also the hread form the ieee.std_textio but it was a mess.
( of course with a hexadecimal data file, AAA, 0000 , etc.. )
Can anyone give me a tip here? Like somesort of template for reading files
and putting the values on some outports?

I agree with you that parsing text is a pain.
Consider declaring native types.
Maybe an array of records,
as a constant or a file.

Related article:
http://groups.google.com/groups?q=records+file_id+my_type


-- Mike Treseler