B
bigcaterpillar@gmail.com
Guest
I synthesis the verilog code .
e.g1. I find so many latches.e.g2. I find a multiplexer
I want to know the difference bewteen them ,such as area,
power,latency and speed .....
verilog code:
input[1:0] sela;
input[63:0] x,mc;
output[63:0]a;
e.g.1.
assign a = ({64{sela[0]}}&x)|({64{sela[1]}}&mc);
e.g.2
always@(sela)
case(sela)
2'b01: a<=x;
2'b10: a<=mc;
default:a<=0;
endcase
e.g1. I find so many latches.e.g2. I find a multiplexer
I want to know the difference bewteen them ,such as area,
power,latency and speed .....
verilog code:
input[1:0] sela;
input[63:0] x,mc;
output[63:0]a;
e.g.1.
assign a = ({64{sela[0]}}&x)|({64{sela[1]}}&mc);
e.g.2
always@(sela)
case(sela)
2'b01: a<=x;
2'b10: a<=mc;
default:a<=0;
endcase