The reset or set test condition for <DecodeOutput> is incomp

[midasyoo]

I'm not good at coding verilog. i'm novice. i'm using ISE7.1i tool.
Below code is decoder that i made. And i synthesized this code with ISE
7.1i.
But, below error message was happened.
I couldn't understand its meaning. --;
What's the wrong?

Any help, or pointers to good docs would be great!
Thanks in advance,



&lt;&lt;&lt; Synthesize &gt;&gt;&gt;

Started process "Synthesize".
===================================================================
* HDL Compilation
*
===================================================================
Compiling verilog file "decoder.v"
Module &lt;decoder&gt; compiled
No errors in compilation
Analysis of file &lt;"decoder.prj"&gt; succeeded.


===================================================================
* HDL Analysis
*
===================================================================
Analyzing top module &lt;decoder&gt;.
SEL = 1
ERROR:Xst:898 - "decoder.v" line 133: The reset or set test condition
for &lt;DecodeOutput&gt; is incompatible with the event declaration in the
sensitivity list.
Set property "resynthesize = true" for unit &lt;decoder&gt;.

Found 1 error(s). Aborting synthesis.
--&gt;

Total memory usage is 82580 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.

Compiling verilog file "decoder.v"



&lt;&lt;&lt; Code &gt;&gt;&gt;

`timescale 1ns / 1ps
module decoder(
//Clock
Clk,
// Reset
RstN,
// Enable
EnN,
// Input
AddrInput,
// Output
DecodeOutput,
//LedInput
LedInput,
//LedOutput
LedOutput
);

/////////////////////////////
// Port Declaration

input Clk;
input RstN;
input EnN;
input [1:0] AddrInput;

output [3:0] LedInput;
output [3:0] LedOutput;
output [3:0] DecodeOutput;
reg [3:0] DecodeOutput;

parameter SEL = 1;

wire EnN;
wire d0, d1, d2, d3;
wire Over;

assign invEnN = ~EnN;


/////////////////////////////
// Port Assign

assign d0 = (SEL == (~AddrInput[1] &amp; ~AddrInput[0])) ? 1'b1 : 1'b0 ;
assign d1 = (SEL == (~AddrInput[1] &amp; AddrInput[0])) ? 1'b1 : 1'b0 ;
assign d2 = (SEL == ( AddrInput[1] &amp; ~AddrInput[0])) ? 1'b1 : 1'b0 ;
assign d3 = (SEL == ( AddrInput[1] &amp; AddrInput[0])) ? 1'b1 : 1'b0 ;


/////////////////////////////
// Decoding Block

always @ (posedge Clk or negedge RstN)
begin : decodingEnable
if (RstN == 1'b1)
begin
DecodeOutput &lt;= 0;
end
else
begin
if (invEnN == 1'b1)
begin
if (d0) begin DecodeOutput &lt;= 1;
end
else if (d1) begin DecodeOutput &lt;= 2;
end
else if (d2) begin DecodeOutput &lt;= 4; end
else if (d3) begin DecodeOutput &lt;= 8;
end
else begin DecodeOutput &lt;= 0;
end
end
else
begin
DecodeOutput &lt;= DecodeOutput + 4'b0001; end
end
end
endmodule