S
shinningstar
Guest
As we all know, verilog 2001 support the useage of "always@*" in the
combination logic block. It's a good news for us because we don't need to
care about the integrity of sensitive list which will cause mismatch
between pre and post simulation.
My question is: Does this useage will impact on the speed of simulation?
combination logic block. It's a good news for us because we don't need to
care about the integrity of sensitive list which will cause mismatch
between pre and post simulation.
My question is: Does this useage will impact on the speed of simulation?