A
Alif Wahid
Guest
A quick explanation of the 'impure' construct/keyword in VHDL would be
much appreciated. My VHDL reference (Rushton's "VHDL for Logic
Synthesis") doesn't seem to provide any explanation for it although I
could have missed it entirely.
Regards,
Alif.
much appreciated. My VHDL reference (Rushton's "VHDL for Logic
Synthesis") doesn't seem to provide any explanation for it although I
could have missed it entirely.
Regards,
Alif.