The following is ILLEGAL Verilog, yes?

[Chris F Clark]

I just want to verify my reading of the standard(s). First, here is
the illegal module. Next, are two corrected versions that implement
the module writer's intent.

-Chris


module m( port[param: 0] ) // illegal line, param not defined yet

parameter param = 1;
input [param: 0] port;
wire [param: 0] port;

endmodule

////////////////////////////////////////////////////////////
// This is a legal 1995 style version of the code

module m( port )

parameter param = 1;
input [param: 0] port;
wire [param: 0] port;

endmodule


////////////////////////////////////////////////////////////
// This is a legal 2001 style version of the code

module m
#(parameter param = 1)
( input [param: 0] port )

endmodule

 

[Larry Doolittle]

In article <sddoepm37xh.fsf@shell01.TheWorld.com>, Chris F Clark wrote:

////////////////////////////////////////////////////////////
// This is a legal 1995 style version of the code

module m( port )

Add a ";" here.

parameter param = 1;
input [param: 0] port;
wire [param: 0] port;

endmodule


////////////////////////////////////////////////////////////
// This is a legal 2001 style version of the code

module m
#(parameter param = 1)
( input [param: 0] port )

Add a ";" here.

endmodule

Both of these versions make it through iverilog's parser,
so you can't be too far off base.

- Larry

 

[Steven Sharp]

Chris F Clark <cfc@shell01.TheWorld.com> wrote in message news:<sddoepm37xh.fsf@shell01.TheWorld.com>...

I just want to verify my reading of the standard(s). First, here is
the illegal module. Next, are two corrected versions that implement
the module writer's intent.

That matches my understanding.