The fastest interface between FPGA's

G

Griva

Guest
Hi,

I'm looking for the fastest interface/standard between two FPGAs.
Have You got any suggestions?

Thnx for answers.

--
Best Regards,
Griva
 
Użytkownik "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> napisał w
wiadomości news:bvt49f$k8h$1@news.tu-darmstadt.de...
Griva <griva@poczta.onet.pl> wrote:
: Hi,

: I'm looking for the fastest interface/standard between two FPGAs.
: Have You got any suggestions?

It depends on reuirements:
- Uni/Bidirectional
- Distance between chips
- Number of connections allowed
...

I think that nearly always it is best to get a bigger FPGA and put
everything into one package.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Click to expand...
Reqiurements:
- Uni/Bi - for me it doesn't matter, could be this and this
- Distance - about 3-5 cm
- Number - about 500 - 700 pins

The biggest FPGA is too small, I have to use 2 or 3 FPGAs and I want to have
the fastest transfer between these chips.

Best Regards,
Griva
 
Griva <griva@poczta.onet.pl> wrote:
: Hi,

: I'm looking for the fastest interface/standard between two FPGAs.
: Have You got any suggestions?

It depends on reuirements:
- Uni/Bidirectional
- Distance between chips
- Number of connections allowed
....

I think that nearly always it is best to get a bigger FPGA and put
everything into one package.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
From a cost standpoint, that is not always true. Also, if you have a
memory intensive application, you get more memory by using two smaller
devices (say XC2V3000's) instead of one larger one (eg XC2V6000). If
you have the luxury of using a chip with the high speed serial i/o,
that will give you rather high bandwidth connections without using up
many pins. Otherwise, you need to refer to the data sheets for each of
the i/o standards supported to see the speeds and what is required to
make it work. Some of the lower voltage swings are faster, but have
special voltage requirements you may not be able to meet. LVDS is
generally faster, at least on longer runs. You may need external
terminators as well, as IIRC, invoking the DCI has a substantial speed
penalty.

Uwe Bonnes wrote:

Griva <griva@poczta.onet.pl> wrote:
: Hi,

: I'm looking for the fastest interface/standard between two FPGAs.
: Have You got any suggestions?

It depends on reuirements:
- Uni/Bidirectional
- Distance between chips
- Number of connections allowed
...

I think that nearly always it is best to get a bigger FPGA and put
everything into one package.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Do you need 500-700 pins at 10 Gb/s ?
How about 622 Mb/s ?
Do you need speed (heavily pipelined design) or low latency (less tolerable
to register delays)?
There are many ways to skin your cat.


"Griva" <griva@poczta.onet.pl> wrote in message
news:bvt5a3$i44$1@nemesis.news.tpi.pl...
Użytkownik "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> napisał
w
wiadomości news:bvt49f$k8h$1@news.tu-darmstadt.de...
Griva <griva@poczta.onet.pl> wrote:
: Hi,

: I'm looking for the fastest interface/standard between two FPGAs.
: Have You got any suggestions?

It depends on reuirements:
- Uni/Bidirectional
- Distance between chips
- Number of connections allowed
...

I think that nearly always it is best to get a bigger FPGA and put
everything into one package.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Reqiurements:
- Uni/Bi - for me it doesn't matter, could be this and this
- Distance - about 3-5 cm
- Number - about 500 - 700 pins

The biggest FPGA is too small, I have to use 2 or 3 FPGAs and I want to
have
the fastest transfer between these chips.

Best Regards,
Griva
Click to expand...
 
I fully agree with Ray.
When it comes to high bandwidth bidir communication, your only cost
effective solution is serial io.
3 to 5 cm is not a big distance, but be aware at 2.5Gbps and above,
PCB design is not very straight forward. Differences in trace length,
cross-over distortion, etc. are things that you will have to deal
with. Robustness of the serdes, easy of programming, jitter tolerance,
.... are very important.

Regards
On Thu, 05 Feb 2004 08:15:07 -0500, Ray Andraka <ray@andraka.com>
wrote:

From a cost standpoint, that is not always true. Also, if you have a
memory intensive application, you get more memory by using two smaller
devices (say XC2V3000's) instead of one larger one (eg XC2V6000). If
you have the luxury of using a chip with the high speed serial i/o,
that will give you rather high bandwidth connections without using up
many pins. Otherwise, you need to refer to the data sheets for each of
the i/o standards supported to see the speeds and what is required to
make it work. Some of the lower voltage swings are faster, but have
special voltage requirements you may not be able to meet. LVDS is
generally faster, at least on longer runs. You may need external
terminators as well, as IIRC, invoking the DCI has a substantial speed
penalty.

Uwe Bonnes wrote:

Griva <griva@poczta.onet.pl> wrote:
: Hi,

: I'm looking for the fastest interface/standard between two FPGAs.
: Have You got any suggestions?

It depends on reuirements:
- Uni/Bidirectional
- Distance between chips
- Number of connections allowed
...

I think that nearly always it is best to get a bigger FPGA and put
everything into one package.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Click to expand...
 
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