'The expression can not be converted to type' error

[A. Kong]

Hi, all,

I wonder if anyone can suggest what actually is wrong with this fragment
of code:

==============================
entity memory is
port(
address: in std_logic_vector(31 downto 0);
write_data : in std_logic_vector(31 downto 0);
MemWrite, MemRead: in std_logic;
clk, reset: in std_logic;
read_data ut std_logic_vector(31 downto 0));
end memory;

architecture behavioral of memory is
type mem_array is array(63 downto 0) of std_logic_vector(31 downto 0);
begin
....
if MemWrite = '0' then
mem_array(addr) := write_data;
else
read_data <= data_mem(addr);
end if;
....
==============================

At the line 'mem_array(addr) := write_data;' xilinx complaints:

Line xx. The expression
can not be converted to type mem_array.

But both write_data and mem_array(addr) are std_logic_vector(31 downto
0). There should be no conversion to mem_array.

I am using Xilinx Project Navigator 4.2Wp3.x

Cheers,
Anthony

 

[Nicolas Matringe]

A. Kong a écrit:

Hi, all,

I wonder if anyone can suggest what actually is wrong with this fragment
of code:
[...]
architecture behavioral of memory is
type mem_array is array(63 downto 0) of std_logic_vector(31 downto 0);
begin
...
if MemWrite = '0' then
mem_array(addr) := write_data;
else
read_data <= data_mem(addr);
end if;
[...]

mem_array is a type, not a signal or a variable. You have to declare an
object (signal or variable) of type mem_array and assign a value to this
object.

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[rickman]

Nicolas Matringe wrote:

A. Kong a écrit:
Hi, all,

I wonder if anyone can suggest what actually is wrong with this fragment
of code:
[...]
architecture behavioral of memory is
type mem_array is array(63 downto 0) of std_logic_vector(31 downto 0);
begin
...
if MemWrite = '0' then
mem_array(addr) := write_data;
else
read_data <= data_mem(addr);
end if;
[...]

mem_array is a type, not a signal or a variable. You have to declare an
object (signal or variable) of type mem_array and assign a value to this
object.

From reading the code, I believe data_mem was supposed to be the array
variable.

One other comment, they way you have put the read inside the else of
your if, it will function like a latch on the output of the memory. If
the if statement is inside a clocked process, it will add a register to
the output of the memory array. That may or may not be what was
intended.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[A. Kong]

rickman wrote:
[snip]

From reading the code, I believe data_mem was supposed to be the array
variable.

One other comment, they way you have put the read inside the else of
your if, it will function like a latch on the output of the memory. If
the if statement is inside a clocked process, it will add a register to
the output of the memory array. That may or may not be what was
intended.

Thanks both of you for your response. It was a typo in the code and I
was too tried to spot the obvious.

Cheers,
AK

 

[Pieter Hulshoff]

"A. Kong" <ahwkong2x1000-at-anti-spam-yahoo.com> wrote:

type mem_array is array(63 downto 0) of std_logic_vector(31 downto
0);
But both write_data and mem_array(addr) are std_logic_vector(31 downto
0). There should be no conversion to mem_array.

mem_array is defined as a TYPE. You can't assign a value to a type.

Regards,

Pieter Hulshoff