The differences between nets and regs in Verilog

[Dave Rich]

Learn about the differences between nets and variables, reg and logic in Verilog and SystemVerilog. http://go.mentor.com/wire-vs-reg

Dave Rich
Mentor Graphics
go.mentor.com/drich

 

On Monday, May 27, 2013 10:02:18 AM UTC-5, Dave Rich wrote:

Learn about the differences between nets and variables, reg and logic in Verilog and SystemVerilog. http://go.mentor.com/wire-vs-reg



Dave Rich

Mentor Graphics

go.mentor.com/drich

Thank You Dave