The difference bewteen RTL and behavioral level

[Kecheng]

I'm very confused about the difference bewteen RTL and behavioral
level. Can anyone give me a Verilog Example to help me to distinguish
which is RTL and which is behavioral level.

Thanks a bunch!

 

[Yottameter]

I'll attempt to answer your question in a simple way, but I think the
main message from the other contributors is that it really doesn't
matter - just get whatever you need to get done as fast as possible with
the highest quality. If you understand that, then you understand verilog.

In answering your question, keep in mind that this is only my opinion.
People in industry use the terms almost interchangably, especially
managers who treat designs as black boxes associated with a delivery
date. Even if I give you an answer that is concise and correct, it will
not matter as the industry is pretty chaotic with regards to definitions.

So now that you are totally demoralized, let's begin.

Verilog code qualifies as RTL to me if it can be synthesized in a
synthesizer from Synopsys, Xilinx, or whatever synthesizer you are
using. If you get no errors from the synthesizer, and you can use the
output of the synthesizer in a product which matches the orignal intent
of the code, then that code is RTL.

Behavioral level refers to verilog code that typically isn't
synthesized. This typically refers to the testbench that wraps around
the RTL code, or a model that is in the RTL code. For instance, if I
have a memory block, I might use a behavioral (also sometimes called
functional) block to represent the memory in my simulations. I probably
wouldn't synthesize it, because in the synth step I would replace it
with a dedicated black box from the memory vendor which was constructed
by hand for optimal timing and functionality. If I have a DLL, I might
exchange the voltage to current convertor for a verilog behavioral
model, but neither Synopsys or Xilinx would synth it, nor would I want
them to. I would lay that out by hand.

With regards to code, RTL might look like:

reg [4:0] myCounter;

always @(posedge clk or negedge rstn)
if (!rstn)
myCounter<=0;
else
myCounter<=myCounter+1;

which (assuming no dumb errors) would synthesize a 5 bit counter that
resets to zero when the rstn signal is asserted low.

The behavioral version of this code can be written in many ways, but the
main point is that it's not synthesizable. Here's one example:

always @(posedge clk or negedge rstn)
//This is really dumb
begin
myCounter=myCounter+1;
if (!rstn)
myCounter=0;
end

Now, I'm sticking my neck out a bit here because I haven't tried either
of these in sim, or synth, but the basic idea I'm trying to get across
is that RTL is synthesizable by a verilog synthesizer, and behavioral
generally isn't. Behavioral is used to either test RTL blocks, or
replace blocks in RTL that would be better constructed using other means.

 

[parag_paul@hotmail.com]

Why is the last example not synthesizable
I dont see a latch here
-Parag