The definition of combinatorial process?

[Weng Tianxiang]

The following topic may be one of the longest debate in vhdl group:
http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/bd9acd78a33d1dae/3de3fe8ea3eec9ad?hl=en&q=combinatorial&lnk=ol&

The debute focus later turns to which is the best way to code: either one sequntial process or two process method, one combinarotial process and one sequential process.

The strange thing is that I cannot even find the word "combinarotial" in VHDL-2002 specification.

I want to grammarly define a combinatorial process which cannot have a clock statement in one of my thinking.

process_statement_part ::=
{ sequential_statement }

sequential_statement ::=
wait_statement
| assertion_statement
| report_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement
| case_statement
| loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement

combinatorial_process_statement_part ::=
{ combinatorial_sequential_statement }

combinatorial_sequential_statement ::=
assertion_statement -- wait_statement is deleted here !!!
| report_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement
| case_statement
| loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement

Am I right?

Weng