The best way to synchronize

[Mike Treseler]

john wrote:

I am posting the RTL view of the Reset circuitry genearted by the
Quatrus II. Please use the following link to view the ciruit
http://img219.imageshack.us/my.php?image=restcircuitryin4.png

Consider instancing the entity,
exactly as I posted it.

-- Mike Treseler

 

[john]

Hi,

I am posting the RTL view of the Reset circuitry genearted by the
Quatrus II. Please use the following link to view the ciruit
http://img219.imageshack.us/my.php?image=restcircuitryin4.png

Thanks
John

 

[john]

On Feb 18, 3:45 pm, Mike Treseler <mike_trese...@comcast.net> wrote:

john wrote:
Please advice which is the most efficient way to synchronize the
external ( hardware ) Reset signal with the clock.

I don't know how efficient it is,
but I use an asynch assert and sync de-assert
something like this.

http://home.comcast.net/~mike_treseler/reset.vhdhttp://home.comcast.net/~mike_treseler/reset.pdf

It's just a two flop shifter, reset_out is preset with reset_in.
A zero is clocked out to de-assert reset_out.

      -- Mike Treseler.

Hi,

I tried your code too but the Quatrus is giving me one flip flop with
shorted D input to Q output. I do not understand why it is doing
that.
Regrads,
John

 

[Mike Treseler]

john wrote:

Please advice which is the most efficient way to synchronize the
external ( hardware ) Reset signal with the clock.

I don't know how efficient it is,
but I use an asynch assert and sync de-assert
something like this.

http://home.comcast.net/~mike_treseler/reset.vhd
http://home.comcast.net/~mike_treseler/reset.pdf

It's just a two flop shifter, reset_out is preset with reset_in.
A zero is clocked out to de-assert reset_out.

-- Mike Treseler.

 

[john]

Hi,

Please advice which is the most efficient way to synchronize the
external ( hardware ) Reset signal with the clock. I am using Quatrus
II 7.2 version. The first piece of code generates a D flip flop , gets
Reset_1 as an input and generates a Reset_out output. The Reset _ 1
and the Reset_output are not directly conencted to each other like
with a wire or compiler is not shorting the input of the flip flop to
the output of the flip flop.

The second piece of code generates the D flip flop and connects input
of the flip flop to the output directly via a wire. I can see that in
the RTL viewer. that the Quatrus is shorting the input of the flip
flop to the output of the flip flop but it works fine too practically.
I am confused which is the right choice because of my lack of VHDL
experience.

ResetProc: Process (DPR_CLK, Reset_switch)
Begin
If ( Reset_switch = '1') Then
Reset_1 <='1';
Reset_2 <='1';
Reset_LED <='1';
elsif rising_edge(DPR_CLK) then
Reset_1 <='0';
Reset_2 <= Reset_1;
Reset_LED <='0';
End If;
Reset_out <= Reset_1;
End process;

OR

ResetProc: Process (DPR_CLK, Reset_switch)
Begin
If ( Reset_switch = '1') Then
Reset_1 <='1'; -- Signal
Reset_2 <='1'; -- Signal
Reset_LED <='1';
elsif rising_edge(DPR_CLK) then
Reset_1 <='0';
Reset_2 <= Reset_1;
Reset_LED <='0';
End If;
End process;
Reset_out <= Reset_2;



Regards,
John

 

[john]

Hello,

I can not use the same entity because the asynchronous reset is the
part of the rest of the VHDL code. The Reset input is the part of the
entity.

Regards,
John

 

[Mike Treseler]

john wrote:

I can not use the same entity because the asynchronous reset is the
part of the rest of the VHDL code. The Reset input is the part of the
entity.

After going to the trouble of making a clean reset,
why would I use the raw one as well?
The reset out port ought to be wired like this:

reset---[reset.vhd]---reset_s---[rest_of_code.vhd]

Your top.vhd would contain wire declarations and instances:

signal reset_s : std_ulogic;

reset_1: entity work.reset
port map (clock => clock, -- [in] top port
reset_in => reset, -- [in] top port
reset_out => reset_s); -- [out] wire

rest_of_code_1: entity work.rest_of_code
port map (clock => clock, -- [in] top port
reset_in => reset_s -- [in] wire
etc



-- Mike Treseler

 

[JK]

Mike,
Asynchronously asserting and sunchronously de-asserting reset can be
done like this??

process(refclk)
begin
if rising_edge(refclk) then
rst_s <= async_rst;
rst_ss <= rst_s;
end if;
end process;

rst_out <= async_rst or rst_ss;

Regards,
JK

 

[Mike Treseler]

JK wrote:

Asynchronously asserting and sunchronously de-asserting reset can be
done like this??
...

The design is incomplete without
an entity and all the processes.

If you are really interested,
run an RTL view and a sim,
and see for yourself.


-- Mike Treseler