A
aushitha
Guest
Hello
I have written a vhdl code for duplicating values.The problem is
in Mentor Graphic Design Architect the assign statement in Verilog
doesnt generate a schematic for my code.So I would like to know if
anybody faced such a problem and over came it.Is there anyother
statement in verilog which can be substituted for assign.Please let me
know.
I have written a vhdl code for duplicating values.The problem is
in Mentor Graphic Design Architect the assign statement in Verilog
doesnt generate a schematic for my code.So I would like to know if
anybody faced such a problem and over came it.Is there anyother
statement in verilog which can be substituted for assign.Please let me
know.