TextIO NCVHDL simulation problem

[Lily]

Hi,

I've got problem with my ALU testbench. the testbench works fine when
i simulate and extract but when i try to view the waveform it is
complaining as below

ncsim> run

Error! TEXTIO error
LINE of length 0 on READ of type CHARACTER

below is my full testbench program. could anybody out there help me
pls ?

thanks a lot.


library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;


entity alu_testbench is
end alu_testbench;

architecture test_alu of alu_testbench is
component alu_testbench
generic(
OPERAND_WIDTH : integer := 8);
Port (
-- The input/ouput interface of the module
S : in std_logic_vector(3 downto 0);
A : in std_logic_vector(OPERAND_WIDTH-1 downto 0);
B : in std_logic_vector(OPERAND_WIDTH-1 downto 0);
Y : out std_logic_vector(OPERAND_WIDTH-1 downto 0);
CI : in std_logic;
C, V, Z : out std_logic
);
end component;


constant clk_period: time := 5 ns;
constant OPERAND_WIDTH : integer := 8;

-- declare math opcode constants
constant ADD : std_logic_vector(3 downto 0) := "0000";
constant SUB : std_logic_vector(3 downto 0) := "0010";
constant INC : std_logic_vector(3 downto 0) := "0001";
constant CMP : std_logic_vector(3 downto 0) := "0011";

-- declare logical opcode constants
constant opAND : std_logic_vector(3 downto 0) := "1100";
constant opOR : std_logic_vector(3 downto 0) := "1101";
constant opXOR : std_logic_vector(3 downto 0) := "1110";
constant opCPL : std_logic_vector(3 downto 0) := "1111";


signal clock : std_logic;
signal rst : std_logic;
signal S : std_logic_vector(3 downto 0);
signal A : std_logic_vector(OPERAND_WIDTH-1 downto 0);
signal B : std_logic_vector(OPERAND_WIDTH-1 downto 0);
signal Y : std_logic_vector(OPERAND_WIDTH-1 downto 0);
signal CI : std_logic;
signal C, V, Z : std_logic;
signal done : std_logic;


for t1 : alu_testbench use entity work.alu_structure;


begin -- behavior
t1 : alu_testbench


port map (
S => S,
A => A,
B => B,
Y => Y,
CI => CI,
C => C,
V => V,
Z => Z
);


-- the clock
clk : process
begin -- process clk
clock <= '0', '1' after 5 ns;
wait for 10 ns;
end process clk;


-- printstatus process

Printstatus : process

file infile : text is in "/elhome/elhh2/NCVHDL/input.txt";
--file outfile : text is out "output.txt";
variable aluinput : std_logic_vector(19 downto 0) := "00000000000000000000";
variable buff : line;

begin
while not (endfile(infile)) loop
readline(infile, buff);
read(buff,aluinput);

A(0) <= aluinput(0);
A(1) <= aluinput(1);
A(2) <= aluinput(2);
A(3) <= aluinput(3);
A(4) <= aluinput(4);
A(5) <= aluinput(5);
A(6) <= aluinput(6);
A(7) <= aluinput(7);

B(0) <= aluinput(8);
B(1) <= aluinput(9);
B(2) <= aluinput(10);
B(3) <= aluinput(11);
B(4) <= aluinput(12);
B(5) <= aluinput(13);
B(6) <= aluinput(14);
B(7) <= aluinput(15);

S(0) <= aluinput(16);
S(1) <= aluinput(17);
S(2) <= aluinput(18);
S(3) <= aluinput(19);

wait until falling_edge(clock);

end loop;
wait;
end process Printstatus;




end test_alu;