Textchio - Improvised tests

[Christiano]

I made a program that makes rapid tests in VHDL using textio.
For example if you have this flip flop to test:

Dff.vhdl:
library ieee;
use ieee.std_logic_1164.all;

entity dffx is
port( d, clk, rst: in std_logic;
q: out std_logic);
end dffx;

architecture behaviour of dffx is
begin
process(rst,clk)
begin
if(rst='1') then
q <= '0';
elsif(clk'event and clk='1') then
q <= d;
end if;

end process;
end behaviour;

Just do this:
$ ghdl -a Dff.vhdl
$ ./testchio dffx d,clk,rst q > testchio.vhdl
$ ghdl -a testchio.vhdl
$ ghdl -e testchio_tb
$ ghdl -r testchio_tb

The first argument is the name of the entity you want to test, the second is a list of inputs separated by commas, and the third is a list of outputs separated by commas.

Then typing the values and go changing inputs improvised, example:
d,clk,rst,q=1110
000
000
d,clk,rst,q=0000
100
100
d,clk,rst,q=1000
110
110
d,clk,rst,q=1101
001
001
d,clk,rst,q=0010

It will show the values and you have the option to change the entries in an improvised way. It's pretty cool to teaching and so on.
For now this works only with std_logic, is very limited.

The code is presented below:

#!/usr/bin/perl

my @ins1 = split(',', $ARGV[1]);
my @ins2 = split(',', $ARGV[2]);

my $subst1 = '';
foreach my $val (@ins1) {
$subst1 = $subst1."$val: in std_logic;";
}

my $subst2 = '';
foreach my $val (@ins2) {
$subst2 = $subst2."$val: out std_logic;";
}
$subst2 = substr $subst2, 0, length($subst2)-1;

my $subst3 = '';
foreach my $val (@ins1) {
$subst3 = $subst3."signal $val: std_logic :='1';";
}

my $subst4 = '';
foreach my $val (@ins2) {
$subst4 = $subst4."signal $val: std_logic;";
}

my $subst5 = '';
foreach my $val (@ins1) {
$subst5 = $subst5."
if($val='1') then
write(dados, string'(\"1\"));
else
write(dados, string'(\"0\"));
end if;
";
}

my $subst6 = '';
foreach my $val (@ins2) {
$subst6 = $subst6."
if($val='1') then
write(dados, string'(\"1\"));
else
write(dados, string'(\"0\"));
end if;
";
}

my $subst7 = '';
my $jk=0;
foreach my $val (@ins1) {
$subst7 = $subst7."
elsif(j=$jk) then
$val <= '0';
";
$jk = $jk+1;
}

my $subst8 = '';
my $jk=0;
foreach my $val (@ins1) {
$subst8 = $subst8."
elsif(j=$jk) then
$val <= '1';
";
$jk = $jk+1;
}

my $subst9 = '';
foreach my $val (@ins1) {
$subst9 = $subst9."$val,";
}
foreach my $val (@ins2) {
$subst9 = $subst9."$val,";
}
$subst9 = substr $subst9, 0, length($subst9)-1;

print 'library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity testchio_tb is

end entity testchio_tb;

architecture behaviour of testchio_tb is
component '.$ARGV[0].'
port ( '.$subst1.$subst2.'

);
end component;


'.$subst3.$subst4.'
begin

UQ1:
dffx port map ('.$ARGV[1].','.$ARGV[2].'

);

-- Stimulus:

main: -- main
process -- Requires ghdl -r <model> --stop-time=<number>ns


variable dados: line;
variable erro: line;
variable j : integer ;
begin -- to stop model execution.

wait for 50 ns;

writeline(output, dados);
write(dados, string\'("'.$subst9.'="));
'.$subst5.$subst6.'

writeline(output, dados);



readline(input, dados);

j := 0;
for i in dados\'range loop
case(dados(i)) is
when \'0\' =>
if(j=-1) then
'.$subst7.'
else
end if;
j := j +1;
when \'1\' =>
if(j=-1) then
'.$subst8.'
else
end if;
j := j+1;
when others => NULL;

end case;
end loop;



end process main;



end behaviour;';