TetraMax need increase fault coverage

L

LR

Guest
Hello all,

I am using Synopsys TetraMax for the first time. The idea is that I (a
recently graduate) am the responsible for a whole chip testing for a
University Program nothing lucrative...I started trying TetraMax in a
very small module that I designed in VHDL, synthesized and scan
inserted with Design Analyzer. There I had no problem and reached 100%
fault coverage. But now I am trying to apply the same process to one
of the real modules that will be placed in the ASIC. It is bigger, has
a scan chain of length 99, after doing in TetraMAX build, DRC...I
applied external ATPG where it ends up showing a result of 8 patterns
and a fault coverage os 21.4%. I then changed the design an inserted
11 scan chains of length 9 instead of an only one and the result was
24% 6 patterns. I created a Matlab program for random pattern
generation that as a results gives a file with the patterns is stil
format (I did this in case there was some error in TetraMax that only
found that small set of patterns) but again there was no change in the
coverage.

Please any idea on how to increase the coverage is welcome because
this results are not unnaceptable.

Thanks in advance,

LR
 

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