testing parameters within generate/endgenerate

[shannon_hill]

In the verilog 2001 examples; I often see cases where, inside a
generate/endgenerate pair,
an if statement, testing the value of a parameter, can cause two
different implementations to be generate'd. I can get this to work
fine.

However, if I attempt to override the parameters of a module
from its instantiation, like

divider #(1,2) c_div ( ... );

the parameters seen by the if statement within the
generate/endgenerate pair (in divider.v) do not get the values set by
the instantiation, but proceeds based on the default values of the
parameters... (in divider.v).

I only have synopsys' VCS 7.2 to try this with...

Is the behavior of parameters in this situation clearly spelled
out somewhere?? Is this expected behavior?

Shannon

 

[Allan Herriman]

On 14 Feb 2006 17:58:14 -0800, "shannon_hill" <sqhill@engineer.com>
wrote:

In the verilog 2001 examples; I often see cases where, inside a
generate/endgenerate pair,
an if statement, testing the value of a parameter, can cause two
different implementations to be generate'd. I can get this to work
fine.

However, if I attempt to override the parameters of a module
from its instantiation, like

divider #(1,2) c_div ( ... );

the parameters seen by the if statement within the
generate/endgenerate pair (in divider.v) do not get the values set by
the instantiation, but proceeds based on the default values of the
parameters... (in divider.v).

I only have synopsys' VCS 7.2 to try this with...

Is the behavior of parameters in this situation clearly spelled
out somewhere??

The LRM.

Is this expected behavior?

No. Sounds like a bug to me.

I often do that sort of thing with Modelsim and XST. Works fine,
although XST does not allow you to mix 2001-style parameters with
pre-2001-style parameters - it's one or the other.

BTW, make sure it's not a bug in your source code first though.

Regards,
Allan

 

[michaelst@gmail.com]

It is VERY important that definition is parameters are going in the
same sequence as you write in the implementation.

For example:
module divider (...);
parameter P1 = 0;
parameter P2 = 0;
parameter P3 = 0;
......
endmodule

Instantiation like:
divider #(1, 2) c_div(...);

will update P1 and P2 but not P3.

Instead you can use following example:
divider #(.P1(1), .P3(2)) c_div(...);
In this case P1 and P2 will be redefined, but P2 remains the same.

 

[rajesh]

its working fine with vcs7.2 ,i had checked with follwing code
module sel(a,b,res);
parameter s1=0;
input [3:0]a,b;
output [4:0] res;
generate
if(s1==0)
add a1(a,b,res);
else
sub s(a,b,res);
endgenerate
endmodule
this parameter s1 is overrriden through the testbench,and add and sub
are two simple submodules doing additon and subtraction of a and b
//THIS IS THE TESTBENCH

module top;
reg [3:0]a,b, a1, b1;
wire [4:0] sum, res;
sel #(.s1(0)) adder (a,b,sum);
sel #(.s1(1)) subtractor (a1,b1,res);
initial
begin
a=10; b=6;
#5 a=5; b=4;
end
initial
begin
$vcdpluson();
end
initial
begin
$monitor($time,"a= %d, b=%d ,sum=%d",a,b,sum);
end

endmodule