testing in verilog

[vittal]

Hi,
What are the testing practices followed in general.
suppose i have to test a i2c bus , then i have create a model and
apply
the stimulus for both DUT and model and verify the outputs (compare).
The main problem i am facing how to design the model.for i2c testing i
was said that
take eeprom as model.please elaborate.
Thanks,
Vittal

 

[Ajeetha]

Hi Vittal,
What you are looking for is "verification" and not "testing" as
per commonly used terminology. Verification requires system level
knowledge, think about where this I2C will be used. Say it is going to
transfer the data from external memory to some internal data processing
unit (in the absence if your architecture, this is a wild guess). What
I2C should ideally do is to guarantee that the data integrity is intact
from sender to receiver side (of-coruse it can be bidirectional as
well). So a "predictor model" is not that hard for it - simply think of
a high level "data transfer" as the transaction and model it that way.

I had created a VMM (see: www.vmm-sv.org, www.systemverilog.us) based
I2C verification model that runs with VCS. It is built on what's
available in OpenCores web site, let me know @ ajeetha <> gmail.com if
interested.

Regards
Ajeetha, CVC
www.noveldv.com

vittal wrote:

Hi,
What are the testing practices followed in general.
suppose i have to test a i2c bus , then i have create a model and
apply
the stimulus for both DUT and model and verify the outputs (compare).
The main problem i am facing how to design the model.for i2c testing i
was said that
take eeprom as model.please elaborate.
Thanks,
Vittal

 

Hi Vittal,

I think you have a homework assignment in a university. If you are not
a student, please ignore what I have written below.

I2C is a simple, 2-wire, half-duplex, low-bitrate communication
protocol. There must be a master device and a slave device. Master
device must be your testbench. Add Verilog tasks in your testbench for
write/read. EEPROM must have I2C model.

It is not good to give more details about implementation. It is your
homework.

Utku.

vittal wrote:
Hi,
What are the testing practices followed in general.
suppose i have to test a i2c bus , then i have create a model and
apply
the stimulus for both DUT and model and verify the outputs (compare).
The main problem i am facing how to design the model.for i2c testing i
was said that
take eeprom as model.please elaborate.
Thanks,
Vittal

 

[vittal]

hi utku
Thanks for guessing.but its not a homework assignment of some
university.
I am a fresher in an electronics industry.I succesfully completed the
problem also.
It required some time ,thats it.I didnt know much about I2C .so why i
had some problems with it.
anyway thanks for ur response.
Vits.
utku.ozcan@gmail.com wrote:

Hi Vittal,

I think you have a homework assignment in a university. If you are not
a student, please ignore what I have written below.

I2C is a simple, 2-wire, half-duplex, low-bitrate communication
protocol. There must be a master device and a slave device. Master
device must be your testbench. Add Verilog tasks in your testbench for
write/read. EEPROM must have I2C model.

It is not good to give more details about implementation. It is your
homework.

Utku.

vittal wrote:
Hi,
What are the testing practices followed in general.
suppose i have to test a i2c bus , then i have create a model and
apply
the stimulus for both DUT and model and verify the outputs (compare).
The main problem i am facing how to design the model.for i2c testing i
was said that
take eeprom as model.please elaborate.
Thanks,
Vittal