Testing a verilog design after synthesis in Xilinx ISE

[kumar]

Hello everyone,
I have a verilog design that is tested with ModelSim simulator and it
works properly. I have synthesized it with Xilinx ISE Tool using XST
and I want to test it(after synthesis) before I can go on with
downloading the BIT file onto a Xilinx FPGA board.
I could not find a way to do it. Can anyone please help me in this
matter?

Thanks a lot,
Kumar