Testbench writing

S

Smith

Guest
Hi all.
I'm now doing a module with verilog which is the binary to bcd
converter. It means it will take a string of binary number( in my case
is 16 bit), and then converse it to be the BCD number.

I've tried to write various pattern of my testbench file for the
module, but every time ends with disappointment.

Hope you all can help me in this. Hope you all can spare some time to
help me figure out what the mistake I had made.
Thanks advance.

Here is my coding for the converter module.

________________________________________
module binary_to_bcd ( clk_i, ce_i, rst_i, start_i, dat_binary_i,
dat_bcd_o, done_o );
parameter BITS_IN_PP = 16; // # of bits of binary input
parameter BCD_DIGITS_OUT_PP = 5; // # of digits of BCD output
parameter BIT_COUNT_WIDTH_PP = 4; // Width of bit counter

// I/O declarations
input clk_i; // clock signal
input ce_i; // clock enable input
input rst_i; // synchronous reset
input start_i; // to start the process of
conversion
input [BITS_IN_PP-1:0] dat_binary_i; // input bus
output [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o; // output bus
output done_o; // to show conversion is done

reg [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;

// Internal signal declarations

reg [BITS_IN_PP-1:0] bin_reg;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_reg;
wire [BITS_IN_PP-1:0] bin_next;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_next;
reg busy_bit;
reg [BIT_COUNT_WIDTH_PP-1:0] bit_count;
wire bit_count_done;

// Functions & Tasks

function [4*BCD_DIGITS_OUT_PP-1:0] bcd_asl;
input [4*BCD_DIGITS_OUT_PP-1:0] din;
input newbit;
integer k;
reg cin;
reg [3:0] digit;
reg [3:0] digit_less;
begin
cin = newbit;
for (k=0; k<BCD_DIGITS_OUT_PP; k=k+1)
begin
digit[3] = din[4*k+3];
digit[2] = din[4*k+2];
digit[1] = din[4*k+1];
digit[0] = din[4*k];
digit_less = digit - 5;
if (digit > 4'b0100)
begin
bcd_asl[4*k+3] = digit_less[2];
bcd_asl[4*k+2] = digit_less[1];
bcd_asl[4*k+1] = digit_less[0];
bcd_asl[4*k+0] = cin;
cin = 1'b1;
end
else
begin
bcd_asl[4*k+3] = digit[2];
bcd_asl[4*k+2] = digit[1];
bcd_asl[4*k+1] = digit[0];
bcd_asl[4*k+0] = cin;
cin = 1'b0;
end

end
end
endfunction

// Module code

// To perform proper shifting, binary and ASL
assign bin_next = {bin_reg,1'b0};
always @(bcd_reg or bin_reg)
begin
bcd_next <= bcd_asl(bcd_reg,bin_reg[BITS_IN_PP-1]);
end


always @(posedge clk_i)
begin
if (rst_i)
begin
busy_bit <= 0; // Synchronous reset
dat_bcd_o <= 0;
end
else if (start_i && ~busy_bit)
begin
busy_bit <= 1;
bin_reg <= dat_binary_i;
bcd_reg <= 0;
end
else if (busy_bit && ce_i && bit_count_done && ~start_i)
begin
busy_bit <= 0;
dat_bcd_o <= bcd_next;
end
else if (busy_bit && ce_i && ~bit_count_done)
begin
bcd_reg <= bcd_next;
bin_reg <= bin_next;
end
end
assign done_o = ~busy_bit;

// Bit counter
always @(posedge clk_i)
begin
if (~busy_bit) bit_count <= 0;
else if (ce_i && ~bit_count_done) bit_count <= bit_count + 1;
end
assign bit_count_done = (bit_count == (BITS_IN_PP-1));

endmodule

____________________________________________________

Here is my written testbench

____________________________________________________

module binary_to_bcd;

reg clk_i, ce_i, rst_i, start_i, dat_binary_i;

wire dat_bcd_o, done_o;

initial begin
clk_i=0; ce_i=0; rst_i=0; start_i=0; dat_binary_i=
16'b0000000000000000;

end
always begin
#5 rst_i=1;
#5 rst_i=0;
#5 ce_i=1;
#5 start_i=1;
#5 dat_binary_i=16'b0000000000000101;
#20 dat_binary_i=16'b0001010000100101;
#20 dat_binary_i=16'b0101100100000011;
#20 dat_binary_i=16'b1000011000100101;
#20 dat_binary_i=16'b1001000010010101;
#20 dat_binary_i=16'b1001001001010101;
end
initial
#130 $finish;

always begin
#1 clk_i=!clk_i;
end
endmodule
______________________________________________
 
Hi Smith,

You have to instantiate the module in the Testbench.

1. Name the testbench differently: ( binary_to_bcd_test)

2. Define dat_binary_i, dat_bcd_o as [15:0] , [19:0] bit register.

3. Instantiate the module:

Final code for testbench:
-------------------

module binary_to_bcd_test;

reg clk_i, ce_i, rst_i, start_i;
reg [15:0] dat_binary_i;

wire [19:0] dat_bcd_o;
wire done_o;

initial begin
clk_i=0; ce_i=0; rst_i=0; start_i=0; dat_binary_i=
16'b0000000000000000;

end
always begin
#5 rst_i=1;
#5 rst_i=0;
#5 ce_i=1;
#5 start_i=1;
#5 dat_binary_i=16'b0000000000000101;
#20 dat_binary_i=16'b0001010000100101;
#20 dat_binary_i=16'b0101100100000011;
#20 dat_binary_i=16'b1000011000100101;
#20 dat_binary_i=16'b1001000010010101;
#20 dat_binary_i=16'b1001001001010101;
end
initial
#130 $finish;

always begin
#1 clk_i=!clk_i;
end

binary_to_bcd binary_to_bcd (
.clk_i (clk_i),
.ce_i (ce_i),
.rst_i( rst_i),
.start_i(start_i),
.dat_binary_i(dat_binary_i),
.dat_bcd_o (dat_bcd_o),
.done_o(done_o)
);
endmodule
 
It seems like a school homework to me :)

Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Smith wrote:
Hi all.
I'm now doing a module with verilog which is the binary to bcd
converter. It means it will take a string of binary number( in my case
is 16 bit), and then converse it to be the BCD number.

I've tried to write various pattern of my testbench file for the
module, but every time ends with disappointment.

Hope you all can help me in this. Hope you all can spare some time to
help me figure out what the mistake I had made.
Thanks advance.

Here is my coding for the converter module.

________________________________________
module binary_to_bcd ( clk_i, ce_i, rst_i, start_i, dat_binary_i,
dat_bcd_o, done_o );
parameter BITS_IN_PP = 16; // # of bits of binary input
parameter BCD_DIGITS_OUT_PP = 5; // # of digits of BCD output
parameter BIT_COUNT_WIDTH_PP = 4; // Width of bit counter

// I/O declarations
input clk_i; // clock signal
input ce_i; // clock enable input
input rst_i; // synchronous reset
input start_i; // to start the process of
conversion
input [BITS_IN_PP-1:0] dat_binary_i; // input bus
output [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o; // output bus
output done_o; // to show conversion is done

reg [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;

// Internal signal declarations

reg [BITS_IN_PP-1:0] bin_reg;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_reg;
wire [BITS_IN_PP-1:0] bin_next;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_next;
reg busy_bit;
reg [BIT_COUNT_WIDTH_PP-1:0] bit_count;
wire bit_count_done;

// Functions & Tasks

function [4*BCD_DIGITS_OUT_PP-1:0] bcd_asl;
input [4*BCD_DIGITS_OUT_PP-1:0] din;
input newbit;
integer k;
reg cin;
reg [3:0] digit;
reg [3:0] digit_less;
begin
cin = newbit;
for (k=0; k<BCD_DIGITS_OUT_PP; k=k+1)
begin
digit[3] = din[4*k+3];
digit[2] = din[4*k+2];
digit[1] = din[4*k+1];
digit[0] = din[4*k];
digit_less = digit - 5;
if (digit > 4'b0100)
begin
bcd_asl[4*k+3] = digit_less[2];
bcd_asl[4*k+2] = digit_less[1];
bcd_asl[4*k+1] = digit_less[0];
bcd_asl[4*k+0] = cin;
cin = 1'b1;
end
else
begin
bcd_asl[4*k+3] = digit[2];
bcd_asl[4*k+2] = digit[1];
bcd_asl[4*k+1] = digit[0];
bcd_asl[4*k+0] = cin;
cin = 1'b0;
end

end
end
endfunction

// Module code

// To perform proper shifting, binary and ASL
assign bin_next = {bin_reg,1'b0};
always @(bcd_reg or bin_reg)
begin
bcd_next <= bcd_asl(bcd_reg,bin_reg[BITS_IN_PP-1]);
end


always @(posedge clk_i)
begin
if (rst_i)
begin
busy_bit <= 0; // Synchronous reset
dat_bcd_o <= 0;
end
else if (start_i && ~busy_bit)
begin
busy_bit <= 1;
bin_reg <= dat_binary_i;
bcd_reg <= 0;
end
else if (busy_bit && ce_i && bit_count_done && ~start_i)
begin
busy_bit <= 0;
dat_bcd_o <= bcd_next;
end
else if (busy_bit && ce_i && ~bit_count_done)
begin
bcd_reg <= bcd_next;
bin_reg <= bin_next;
end
end
assign done_o = ~busy_bit;

// Bit counter
always @(posedge clk_i)
begin
if (~busy_bit) bit_count <= 0;
else if (ce_i && ~bit_count_done) bit_count <= bit_count + 1;
end
assign bit_count_done = (bit_count == (BITS_IN_PP-1));

endmodule

____________________________________________________

Here is my written testbench

____________________________________________________

module binary_to_bcd;

reg clk_i, ce_i, rst_i, start_i, dat_binary_i;

wire dat_bcd_o, done_o;

initial begin
clk_i=0; ce_i=0; rst_i=0; start_i=0; dat_binary_i=
16'b0000000000000000;

end
always begin
#5 rst_i=1;
#5 rst_i=0;
#5 ce_i=1;
#5 start_i=1;
#5 dat_binary_i=16'b0000000000000101;
#20 dat_binary_i=16'b0001010000100101;
#20 dat_binary_i=16'b0101100100000011;
#20 dat_binary_i=16'b1000011000100101;
#20 dat_binary_i=16'b1001000010010101;
#20 dat_binary_i=16'b1001001001010101;
end
initial
#130 $finish;

always begin
#1 clk_i=!clk_i;
end
endmodule
______________________________________________
Click to expand...
 
hi, krishnan
Thanks for pointing out the mistake i made to me
It helps me a lots

Best regards,
smith
 
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