testbench question

[Salman]

I need to generate a data packets of 16-bit data that is random in
value and varies between various lengths per packet and also can be
from 8 different sources. How should I write it in VHDL? Using a
procedure, function or a bus functional model? Any good examples?

 

[Mike Treseler]

Salman wrote:

I need to generate a data packets of 16-bit data that is random in
value and varies between various lengths per packet and also can be
from 8 different sources. How should I write it in VHDL?

With an editor and vhdl simulator.

Using a procedure, function or a bus functional model?
yes yes maybe

Any good examples?

Not exactly, but the testbench here:
http://home.comcast.net/~mike_treseler/
generates random bytes and shifts them out uart style.
The functions randomize and loopback_mux might be
of interest.

-- Mike Treseler