Testbench question - how to get to a wire inside my design i

[Travis]

Hi, I'm trying to take a look at a wire or variable inside my module
under test.

How can I access it from my test bench, when it is not a variable that
I'm outputting from that module?

Thanks

 

[sandeep]

On Nov 14, 2:52 pm, Travis <TRAy...@gmail.com> wrote:

Hi, I'm trying to take a look at a wire or variable inside my module
under test.

How can I access it from my test bench, when it is not a variable that
I'm outputting from that module?

Thanks

Hi
I think Verilog support hierachical access. You can use it.
For eg DUT name is A and it is instantiated in test bench U_A.
then any wire and reg can be access in test bench by
U_A.X
U_A.reg_name
etc..
regards

 

[LittleAlex]

On Nov 13, 11:52 pm, Travis <TRAy...@gmail.com> wrote:

Hi, I'm trying to take a look at a wire or variable inside my module
under test.

How can I access it from my test bench, when it is not a variable that
I'm outputting from that module?

Thanks

All signals can be accessed via <moduleA>/<moduleB>/netname - the
exact syntax changes from simulator to simulator (some are case
sensitive, some care about path separators, etc.)

Fastest way is call up your design with the signal trace GUI, and see
what the full signal name is in the GUI.

Or do a dump all from your bench, and see what the net name is in the
VCD.