Testbench in C

[Dominique LUONG]

Hi All,

I am learning how to write testbench in C language. I usually use
verilog to write testbenches, but i have to move to C.
What i understand is i have to make a pli wrapper around the verilog
tasks, by doing that i will use C function for calling the verilog ones.

But i am quite lost, anyone can show me a little example ?

Thanks for any help,
Dominique
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[Guenter]

Dominique LUONG wrote:

Hi All,

I am learning how to write testbench in C language. I usually use
verilog to write testbenches, but i have to move to C.
What i understand is i have to make a pli wrapper around the verilog
tasks, by doing that i will use C function for calling the verilog ones.

But i am quite lost, anyone can show me a little example ?

You will get some good resources when googleing for Verilog PLI.

One I have bookemarked is this one:

http://www.project-veripage.com/chap1_2.php


Hope that helps.

Guenter

 

[EdA]

Dominique LUONG wrote:

Hi All,

I am learning how to write testbench in C language. I usually use
verilog to write testbenches, but i have to move to C.
What i understand is i have to make a pli wrapper around the verilog
tasks, by doing that i will use C function for calling the verilog ones.

But i am quite lost, anyone can show me a little example ?

Dominique,

Have a look at Teal and Truss, a free open source C++ framework for
writing verification code:

http://www.trusster.com/

Good luck,
/Ed

 

[mjl296@hotmail.com]

Depending on the complexity of what you're doing, it may be worth
considering using SystemC.

Pure C/C++ code can have timing added using SystemC and can then be
co-simulated with your Verilog if your simulator allows it (Mentor and
Cadence tools certainly allow this).

In a project I worked on recently we were able to model the entire
system in C++, which allowed software development and performance
characterisation to begin. We then wrapped each module in SystemC to
provide timing-approximate behaviour. When the Verilog for a module was
completed it could replace its SystemC implementation in the
simulation.

The technique was very powerful. We wrote a paper on it, available
here...

http://www.mentor.com/products/fv/news/upload/ignios_css.pdf


EdA wrote:

Dominique LUONG wrote:
Hi All,

I am learning how to write testbench in C language. I usually use
verilog to write testbenches, but i have to move to C.
What i understand is i have to make a pli wrapper around the verilog
tasks, by doing that i will use C function for calling the verilog ones.

But i am quite lost, anyone can show me a little example ?

Dominique,

Have a look at Teal and Truss, a free open source C++ framework for
writing verification code:

http://www.trusster.com/

Good luck,
/Ed

 

[mmintz@gmail.com]

Hi Dominique,

To follow-up on Ed's post, Teal is tiny; only 10 or so source files.
SystemC is huge, having thousands of source files. Teal contains the
basic components of a testbench in C++, providing a C++/Verilog gasket,
logging, stable random number generation and arbitrary length 4-state
registers, and threading. SystemC is mainly a modeling library, not a
verification library.

Truss sits on top of Teal and is the VMM/AVM like methodology. It
provides channels, the top level component "dance" and some register
macros that can be used to run software driver code.

I also have co-authored a book on the philosophy of writing testbenches
in C++/OOP. The amazon pointer is:
http://www.amazon.com/gp/product/0387255435/sr=8-1/qid=1146003504/ref=sr_1_1/104-3677833-6263957?%5Fencoding=UTF8

Feel free to contact me off list (mike@trusster.com)

Take Care,
Mike Mintz
Harvard, MA

 

[i.am.ahung@gmail.com]

Regarding the earlier post about making a gasket to connect C to
Verilog:

SystemC is built on C++ and is very robust (you don't want to be
debugging language bugs days before tapeout). You can hook up SystemC
to Verilog with gaskets completely written in C using PLI's. You just
need a Verilog 2001 compiler. I am working on posting my code on the
net......

stay tuned.... and comments appreciated

anthony

 

On 23 פברואר, 02:11, "i.am.ah...@gmail.com" <i.am.ah...@gmail.com>
wrote:

Regarding the earlier post about making a gasket to connect C to
Verilog:

SystemC is built on C++ and is very robust (you don't want to be
debugging language bugs days before tapeout). You can hook up SystemC
to Verilog with gaskets completely written in C using PLI's. You just
need a Verilog 2001 compiler. I am working on posting my code on the
net......

stay tuned.... and comments appreciated

anthony

Why mixing both verilog and systemC.
I started to study systemC (h—p://bknpk.no-ip.biz/MiscellaneousHW/
MiscellaneousHW.html), because I do sometimes project on my spare
time. Usually I use free simulators like (icarus and GHDL), which are
slow, compared with commercial ones. So for the very reason of fast
simulation, systemC (without mixing with other HDLs) is very
attractive for me.

 

[Jeremy Bennett]

On Sun, 22 Feb 2009 21:15:49 -0800, bknpk wrote:

On 23 פברואר, 02:11, "i.am.ah...@gmail.com" <i.am.ah...@gmail.com
wrote:
Regarding the earlier post about making a gasket to connect C to
Verilog:

SystemC is built on C++ and is very robust (you don't want to be
debugging language bugs days before tapeout). You can hook up SystemC
to Verilog with gaskets completely written in C using PLI's. You just
need a Verilog 2001 compiler. I am working on posting my code on the
net......

stay tuned.... and comments appreciated

anthony

Why mixing both verilog and systemC.
I started to study systemC (h—p://bknpk.no-ip.biz/MiscellaneousHW/
MiscellaneousHW.html), because I do sometimes project on my spare time.
Usually I use free simulators like (icarus and GHDL), which are slow,
compared with commercial ones. So for the very reason of fast
simulation, systemC (without mixing with other HDLs) is very attractive
for me.

Hi Anthony,

The mainstream simulators all provide SystemC interfaces, so you don't
need PLI gaskets.

You could consider generating SystemC from your Verilog, so you entire
system in in a single language. There are commercial tools from ARC
(VTOC) and Carbon Design Systems (ModelStudio), and there is the free
open source tool, Verilator (www.veripool.org/wiki/verilator).

If you don't like SystemC, these tools will all generate plain C++, which
is easy enough to link to C.

It's not the same as event-driven simulation - the generated models are 2-
state, cycle accurate, zero delay, i.e. synthesis semantics. However the
trade off can be substantially better performance, and for applications
such as functional system verification, legacy reuse in architectural
exploration or low-level firmware development they are ideal.

I've written a number of application notes and tutorials on modeling in
SystemC, including the use of tools like Verilator:

http://www.embecosm.com/download/index.html

HTH,


Jeremy

 

[Mike]

Hi Anthony,

You might also want to consider a small open source gasket that I
wrote called Teal. It's only a few source files and works with five
simulators. You can download the latest on www.trusster.com

I am working on a systemC Teal as well, to allow users to connect into
VHDL.

Take Care,
Mike Mintz
www.trusster.com

co-author, "Hardware Verification with C++" and "Hardware Verification
with Systemverilog"

 

[i.am.ahung@gmail.com]

Hi Jeremy,

I know I dont need PLI gaskets if I have money. But in this market,
everyone is trying to save on EDA tools. The SystemC support you refer
to is an upgrade on verilog-2001. that costs money... I've been there,
done that and management doesn't want to hear about upgrades. Also all
of the major EDA companies use different methods for systemC support,
and so it makes it prohibitive to move from one vendor to another.
I've worked in companies that tried that... I am talking about weeks
and months of work to port....

so I emphasize this is a cost saving solution for existing verilog
designs, changing design tools is another story, verilog seems like it
is here to stay though

anthony

Why mixing both verilog and systemC.
I started to study systemC (h—p://bknpk.no-ip.biz/MiscellaneousHW/
MiscellaneousHW.html), because I do sometimes project on my spare time.
Usually I use free simulators like (icarus and GHDL), which are slow,
compared with commercial ones. So for the very reason of fast
simulation, systemC (without mixing with other HDLs) is very attractive
for me.

Hi Anthony,

The mainstream simulators all provide SystemC interfaces, so you don't
need PLI gaskets.

You could consider generating SystemC from your Verilog, so you entire
system in in a single language. There are commercial tools from ARC
(VTOC) and Carbon Design Systems (ModelStudio), and there is the free
open source tool, Verilator (www.veripool.org/wiki/verilator).

If you don't like SystemC, these tools will all generate plain C++, which
is easy enough to link to C.

It's not the same as event-driven simulation - the generated models are 2-
state, cycle accurate, zero delay, i.e. synthesis semantics. However the
trade off can be substantially better performance, and for applications
such as functional system verification, legacy reuse in architectural
exploration or low-level firmware development they are ideal.

I've written a number of application notes and tutorials on modeling in
SystemC, including the use of tools like Verilator:

http://www.embecosm.com/download/index.html

HTH,

Jeremy

 

Hi
I used system c for the follwoing project and was very happy with
results:
'VHDL, verilog, design, verification, scripts, ...'
(http://bknpk.no-ip.biz/First_SCV/aisTB.html)


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