V
VHDL User
Guest
Hi all,
Suppose I want to write a testbench for a design that simulates the
design for a suffciently long time,so that wait for <t> statements are
obv. inadequate .Will a statement
wait;
do the job?
as in causing simulation to run forever?
An y other ideas as to how a long simulation time may be met ?
Suppose I want to write a testbench for a design that simulates the
design for a suffciently long time,so that wait for <t> statements are
obv. inadequate .Will a statement
wait;
do the job?
as in causing simulation to run forever?
An y other ideas as to how a long simulation time may be met ?