testbench check or wait on signal inside a componen without

Hello Group,

In Verilog is it possible to wait or check signales without
any port declaration. for example:

wait (post_testbench.i_post_top.i_post_bsp.error_frame )

where post_top is the top entity, i_post_bsp is an instanciated
component and error_frame is a signal without any port
declaration.

best regards

Micky

 

[Ajeetha]

What you are looking for is a way to do hierarchical referencing in
VHDL, as such VHDL doesn't support it (yet, some proposal is in
VHDL-200X, see http://www.eda.org/vhdl-200x/vhdl-200x-ft/). However,
there are several ways, easiest I would say is to take your simulator's
help - Modelsim has SignalSpy, NC has NC-Mirror, VCS-MX - hdl_xmr etc.
I some time back wrote a simple package to keep TB code independent
(atelast pseduo-independent) of simulator, please see:
http://www.verificationguild.org/modules.php?name=Downloads&d_op=getit&lid=11

http://www.noveldv.com/eda/probe.zip

Also see VHDL FAQ:
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html
HTH
Ajeetha
www.noveldv.com

 

[micky]

Hello Ajeetha

thank you for your good answer.

best regards