Guest
FPGA development efficiency and quality is extremely dependent on the structure and quality of your TB architecture. Verification time could easily differ by a factor of 2 or 3 for medium to high complexity modules/FPGAs - or even for low complexity design with cycle related corner cases.
We all know that the design architecture is critical for an FPGA or a complex module, but most designers seem to ignore that knowledge when it comes to making a good VHDL testbench.
UVVM (Universal VHDL Verification Component Framework Methodology) is free and Open source and provides a very structured VHDL testbench architecture for modules and FPGAs of any complexity. The testbench architecture is very easy to understand, and writing testcases is no problem for an FPGA, HW or SW designer.
We have written a series of 3 brief articles that takes you just a few minutes to read and gives you a good understanding of why UVVM is a game changer with respect to testbench architecture, overview, understanding, maintenance, etc.
You can download the articles from
Bitvis.no: http://bitvis.no/products/uvvm-vvc-framework/
or LinkedIn: https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyone-espen-tallaksen?trk=hp-feed-article-title-publish
Due to the figures and formatting it cannot be properly posted on comp.lang..vhdl.
We all know that the design architecture is critical for an FPGA or a complex module, but most designers seem to ignore that knowledge when it comes to making a good VHDL testbench.
UVVM (Universal VHDL Verification Component Framework Methodology) is free and Open source and provides a very structured VHDL testbench architecture for modules and FPGAs of any complexity. The testbench architecture is very easy to understand, and writing testcases is no problem for an FPGA, HW or SW designer.
We have written a series of 3 brief articles that takes you just a few minutes to read and gives you a good understanding of why UVVM is a game changer with respect to testbench architecture, overview, understanding, maintenance, etc.
You can download the articles from
Bitvis.no: http://bitvis.no/products/uvvm-vvc-framework/
or LinkedIn: https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyone-espen-tallaksen?trk=hp-feed-article-title-publish
Due to the figures and formatting it cannot be properly posted on comp.lang..vhdl.