testbech problem

[Marwan]

Peace,

I have been trying to get this simple test setup to work so I can move
on to more complicated designs... but it has been taking lots of time
and just not working for me... if anyone can see what the problem is,
please comment...

The top level module which instantiates the unit under test.

*****************************************************************************
`timescale 1ns / 1ps
module test_top3();

wire [3:0] out;
integer row;// reg does not seem to work for me
integer col;//"""""
reg clk;

test5 inst1(
.row(row),
.col(col),
.clk(clk),
.out(out)
);

reg [3:0] memo5 [0:3][0:3];

initial
begin
clk = 0;
forever
begin
#2 clk = ~clk;
end
end

always@(posedge clk)
begin
for (row=0;row<=3;row=row+1)
begin
for (col=0;col<=3;col=col+1)
begin
memo5[row][col] = out;
end//for
end//for
$finish;
end
endmodule

************************************************************

The unit under test

*************************************************************

`timescale 1ns / 1ps

module test5(
row,
col,
clk,
out
);

reg [3:0] memt5 [0:3][0:3];

//inputs
input row;
wire [31:0] row;// as integer is default 32 bit on 32 bit systems
input col;
wire [31:0] col;
input clk;
//outputs
output out;
reg [3:0] out;

integer i,j,k;

initial
begin
k = 0;
for (i=0;i<=3;i=i+1)
begin
for (j=0;j<=3;j=j+1)
begin
memt5[j]=k;
k=k+1;
end
end
end//initial

always@(posedge clk)
begin
out <= memt5[row][col];
end
endmodule

 

[Yottameter]

I see two problems, I've pasted corrected code below.

Problem #1: You have a $finish in an always block. After the first
positive edge of clock, it's over.Maybe you intended that, maybe not.

Problem #2: It looks like you are trying to initialize a memory, and
then print out the values on every clock. I've adapted it with the
signals new_row and new_col so that it will work. The problem is that
your row and col loop in the test_top3 module will execute in delta
time, which is triggered by the event posedge clk. Since your block is
triggering off the event posedge clk, the for loop happens without any
effective values changing on row and col between clocks. You need row
and col to change on every clock edge, I've shown an example below.



`timescale 1ns / 1ps
module test_top3();

wire [3:0] out;
integer row;// reg does not seem to work for me
integer col;//"""""
reg clk;

reg [1:0] new_row=0;
reg [1:0] new_col=0;
test5 inst1(
.row(new_row),
.col(new_col),
.clk(clk),
.out(out)
);

reg [3:0] memo5 [0:3][0:3];
initial
begin
clk = 0;
forever
begin
#2 clk = ~clk;
end
end

always@(posedge clk)
begin
new_row=new_row+1;
if (new_row==0) new_col=new_col+1;
for (row=0;row<=3;row=row+1)
begin
for (col=0;col<=3;col=col+1)
begin
memo5[row][col] = out;
end//for
end//for

end

endmodule


`timescale 1ns / 1ps

module test5(
row,
col,
clk,
out
);

reg [3:0] memt5 [0:3][0:3];

//inputs
input [31:0] row;
wire [31:0] row;// as integer is default 32 bit on 32 bit systems
input [31:0] col;
wire [31:0] col;
input clk;
//outputs
output out;
reg [3:0] out;

integer i,j,k;

initial
begin
k = 0;
for (i=0;i<=3;i=i+1)
begin
for (j=0;j<=3;j=j+1)
begin
memt5[j]=k;
k=k+1;
end
end
end//initial

always@(posedge clk)
begin
out <= memt5[row][col];
$display("%d:%d value:%d", row, col, memt5[row][col]);
end
endmodule

 

[Marwan]

Thank you for your time.. I will analyse and test the code and try to
understand my errors in logic.

Peace..