Test vectors for emulator.

[Slawek]

Hello!
My question is:

What is the most popular technique of producing and applying test vectors to
emulated design?
I assume that one of the following solutions can be used:

1. Dumping test vectors from behavioral testbench during simulation.
Applying from a file to emulated design.
2. Designing RTL testbench and emulating along with the design. Obtaining
PASSED/FAILED status from emulator.
3. Connecting emulator to real system (dealing with reduced speed (1 MHz) of
the emulated design).
4. Others?

I know that many engineers put the big emulator boxes in a corner and use
them most often as a stool ~.
Hopefully, someone has other experience and would like to share it with me.

Thanks in advance!
Slawek

 

[Rajkumar Kadam]

On May 11, 1:19 pm, "Slawek" <n...@pulselogic.com.pl> wrote:

Hello!
My question is:

What is the most popular technique of producing and applying test vectors to
emulated design?
I assume that one of the following solutions can be used:

1. Dumping test vectors from behavioral testbench during simulation.
Applying from a file to emulated design.
2. Designing RTL testbench and emulating along with the design. Obtaining
PASSED/FAILED status from emulator.
3. Connecting emulator to real system (dealing with reduced speed (1 MHz) of
the emulated design).
4. Others?

I know that many engineers put the big emulator boxes in a corner and use
them most often as a stool ~.
Hopefully, someone has other experience and would like to share it with me.

Thanks in advance!
Slawek

It depends for what you are emulating the design for.
In ASIC world we emulate the design
1. To get more verification mileage
2. To have a real s/w code running on it for validating our
assumptions in hardware.
I have never used the first option as mentioned by you, but have ended
up using the same testbench to run the test cases
on RTL design as well as Emulated design.
Surely i have used the other 2 options mentioned by you.

Rajkumar...

 

[Slawek]

Thanks, I fully agree that first option is not useful. Maybe to check if
emulator works correctly.
I want to use emulation to improve verification process and find bugs
undetected by behavioral testbench.
Connecting emulator to real system or modeling the system in emulation is a
better choice.

Best Regards,
Slawek

"Rajkumar Kadam" <sh...@yahoo.com> wrote

On May 11, 1:19 pm, "Slawek" <n...@pulselogic.com.pl> wrote:
Hello!
My question is:

What is the most popular technique of producing and applying test vectors
to
emulated design?
I assume that one of the following solutions can be used:

1. Dumping test vectors from behavioral testbench during simulation.
Applying from a file to emulated design.
2. Designing RTL testbench and emulating along with the design. Obtaining
PASSED/FAILED status from emulator.
3. Connecting emulator to real system (dealing with reduced speed (1 MHz)
of
the emulated design).
4. Others?

I know that many engineers put the big emulator boxes in a corner and use
them most often as a stool ~.
Hopefully, someone has other experience and would like to share it with
me.

Thanks in advance!
Slawek

It depends for what you are emulating the design for.
In ASIC world we emulate the design
1. To get more verification mileage
2. To have a real s/w code running on it for validating our
assumptions in hardware.
I have never used the first option as mentioned by you, but have ended
up using the same testbench to run the test cases
on RTL design as well as Emulated design.
Surely i have used the other 2 options mentioned by you.

Rajkumar...