M
meenz
Guest
Hi..
I have developed an RTL for APB slave interface whch receives ( PDATA,
PADDR etc) from a master and writes the data into a memory. I need to
test this design by using it as a part of a bigger design... Maybe the
master.Could anybody suggest examples of easily available simulation
models for the Master which i can use for my testing
I have developed an RTL for APB slave interface whch receives ( PDATA,
PADDR etc) from a master and writes the data into a memory. I need to
test this design by using it as a part of a bigger design... Maybe the
master.Could anybody suggest examples of easily available simulation
models for the Master which i can use for my testing