test pattern

I am still learning VHDL and need some help please! This is what i
have

clk: in std_logic;
data : in std_logic_vector ( 3 downto 0);
data_out: out std_logic_vector (3 downto 0);

clock is running at 20 MHz and data is synchronized with the clock.

if data is in this order "1111", "1010" "1111", "xxxx" than, data out
is "xxxx". So basically I have to look at the data pattern back to
back and then activate my output..if pattern matches, "1111", "0xa"
and "0xb", output is good to go, else have just wait...

I was thinking to have data stored in FIFO and the have some sort of
state machine to look for test pattern..but not sure if that's the
best of doing this...any advice???

 

[LittleAlex]

On Jan 14, 8:33 am, marts...@gmail.com wrote:

I am still learning VHDL and need some help please! This is what i
have

clk: in std_logic;
data : in std_logic_vector ( 3 downto 0);
data_out: out std_logic_vector (3 downto 0);

clock is running at 20 MHz and data is synchronized with the clock.

if data is in this order "1111", "1010" "1111", "xxxx" than, data out
is "xxxx". So basically I have to look at the data pattern back to
back and then activate my output..if pattern matches, "1111", "0xa"
and "0xb", output is good to go, else have just wait...

I was thinking to have data stored in FIFO and the have some sort of
state machine to look for test pattern..but not sure if that's the
best of doing this...any advice???

If I understand your question, you are looking for the sequence 'F'
'A' 'B', and if found, output the data.

This is a classic state-machine learning/homework study exercise.

There is no need to store the codes while waiting for the pattern.
When you get to the 'found' state, you know what the 3 previous codes
are.

That should be enough to get you started.

AL