Test bench

V

Vitaliy

Guest
Hi,
I'm trying to simulate this in Cadence:
http://www.csee.umbc.edu/help/VHDL/samples/bmul32.vhdl

I don't have any problems with that,I can compile the files using
"ncvhdl -v93". I can also import the files in Synopsis and get gate
level as expected.

However, when I try to compile
http://www.csee.umbc.edu/help/VHDL/samples/bmul32_test.vhdl
I get this error.
ncvhdl: 05.10-p004: (c) 1995-2003 Cadence Design Systems, Inc.
ncvhdl_p: *internal* (expecting FUNCTION of PROCEDURE).
Please contact Cadence Design Systems about this problem and provide
enough information to help us reproduce is it.

I'm really stuck on this. Any help would be much appreciated.
 
For one thing....

procedure my_printout(a : std_logic_vector(31 downto 0);
b : std_logic_vector(31 downto 0);
prod: std_logic_vector(63 downto 0)) is

You need to declare the direction of these signals in a procedure. ie.

procedure my_printout(a : IN std_logic_vector(31 downto 0);

I am not sure if that is the whole issue or not- but that is what jumps
out.
 
Thanks. I'll try that tomorrow and post the result if that was enough
to solve the problem.


wpiman@aol.com wrote:
For one thing....

procedure my_printout(a : std_logic_vector(31 downto 0);
b : std_logic_vector(31 downto 0);
prod: std_logic_vector(63 downto 0)) is

You need to declare the direction of these signals in a procedure. ie.

procedure my_printout(a : IN std_logic_vector(31 downto 0);

I am not sure if that is the whole issue or not- but that is what jumps
out.
Click to expand...
 
Vitaliy wrote:

I'm really stuck on this. Any help would be much appreciated.
Click to expand...

Both compile fine when I do this.

-- a1: entity WORK.add32 port map(sum_in, bb, cin, psum, cout);
-- a2: entity WORK.fadd port map(sum_in(31), topbit, cout,topout,nc1);

-- Mike Treseler
 
Mike,
But would it make sense to modify source file to get the test bench to
work? Because source file seems to be fine, at least based on what I
see in Synopsis, and if those two lines are commented out, wouldn't
that change the functionality (btw, did you create WORK subdirectory?
depending on whether you use Linux or Windows(does Cadence even run on
Windows? not sure), you might need it). And did you have those two
files (fadd.vhdl and add32.vhdl) in the same directory as bmul32.vhdl?
Because that could be a reason bmul32.vhdl did not compile.
Thanks for the help, I will try that tomorrow,


Mike Treseler wrote:
Vitaliy wrote:

I'm really stuck on this. Any help would be much appreciated.


Both compile fine when I do this.

-- a1: entity WORK.add32 port map(sum_in, bb, cin, psum, cout);
-- a2: entity WORK.fadd port map(sum_in(31), topbit, cout,topout,nc1);

-- Mike Treseler
Click to expand...
 
Vitaliy wrote:

But would it make sense to modify source file to get the test bench to
work?
Click to expand...
Step one is to find the error.

And did you have those two
files (fadd.vhdl and add32.vhdl) in the same directory as bmul32.vhdl?
Click to expand...
Did you?
Those were not mentioned in your posting.

-- Mike Treseler
 
Yes, I did.

Sorry, missed it in the first post.

Here is the code for fadd.vhdl
library IEEE;
use IEEE.std_logic_1164.all;

entity fadd is -- full adder stage, interface
port(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end entity fadd;

architecture circuits of fadd is -- full adder stage, body
begin -- circuits of fadd
s <= a xor b xor cin after 1 ns;
cout <= (a and b) or (a and cin) or (b and cin) after 1 ns;
end architecture circuits; -- of fadd

here is the code for add32.vhdl

library IEEE;
use IEEE.std_logic_1164.all;
entity add32 is -- simple 32 bit ripple carry adder
port(a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
cin : in std_logic;
sum : out std_logic_vector(31 downto 0);
cout : out std_logic);
end entity add32;

architecture circuits of add32 is
signal c : std_logic_vector(0 to 30); -- internal carry signals
begin -- circuits of add32
a0: entity WORK.fadd port map(a(0), b(0), cin, sum(0), c(0));
stage: for I in 1 to 30 generate
as: entity WORK.fadd port map(a(I), b(I), c(I-1) , sum(I),
c(I));
end generate stage;
a31: entity WORK.fadd port map(a(31), b(31), c(30) , sum(31), cout);
end architecture circuits; -- of add32
 
Vitaliy wrote:
Yes, I did.

Sorry, missed it in the first post.
Here is the code for fadd.vhdl
here is the code for add32.vhdl
Click to expand...
That significantly improves the performance.

-- Mike Treseler
__________________________
69 steptoe Wed Nov 23 /evtfs/home/tres/vhdl/play > vsim -c bmul32_test
Reading /steptoe/usr1/modeltech/tcl/vsim/pref.tcl
# Loading /steptoe/usr1/modeltech/linux/../std.standard
# Loading /steptoe/usr1/modeltech/linux/../std.textio(body)
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_textio(body)
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_arith(body)
# Loading work.bmul32_test(circuits)
# Loading work.bmul32(circuits)
# Loading work.badd32(circuits)
# Loading work.add32(circuits)
# Loading work.fadd(circuits)
VSIM 1> run 1 us
# Driver starting.
# a=11111111, b=11111111, prod=0123456787654321, cntr=0001, at=319 ns
#
# a=22222222, b=22222222, prod=048D159E0C83FB73, cntr=0010, at=639 ns
#
# a=44444444, b=44444444, prod=1234567876543210, cntr=0100, at=959 ns
#
VSIM 2>
 
I have a feeling that my school doesn't have all the proper
libraries/licenses then.
Thank You, Mike.
 
Vitaliy,
Your syntax looks fine. Perhaps you found a tool bug.
None the less you still have to get your work done, so
here are some suggestions.

First if you are using vhdl-93 on the design, use vhdl-93
compile switches for the testbench also.

Next I would check the line number on which the error is being
reported. I am guessing that it is:
end my_printout;
Click to expand...
The syntax for this is:
vhdl-87: end [designator] ;
vhdl-93: end [subprogram_kind] [designator] ;


Given the error message you presented, it seems that
when the compiler is seeing the subprogram designator
(my_printout) it is also expecting it to be preceded
with the subprogram_kind (procedure).

If you are compiling everything with vhdl-93, then try
the following:
end procedure my_printout ;

If the above does not work, or you want to be compatible
with vhdl-87, or you hate typing, you might want to try:
end ;

Cheers,
Jim



Hi,
I'm trying to simulate this in Cadence:
http://www.csee.umbc.edu/help/VHDL/samples/bmul32.vhdl

I don't have any problems with that,I can compile the files using
"ncvhdl -v93". I can also import the files in Synopsis and get gate
level as expected.

However, when I try to compile
http://www.csee.umbc.edu/help/VHDL/samples/bmul32_test.vhdl
I get this error.
ncvhdl: 05.10-p004: (c) 1995-2003 Cadence Design Systems, Inc.
ncvhdl_p: *internal* (expecting FUNCTION of PROCEDURE).
Please contact Cadence Design Systems about this problem and provide
enough information to help us reproduce is it.

I'm really stuck on this. Any help would be much appreciated.
Click to expand...

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Vitaliy,
You also might ask your prof or system admins where the
current version of the tools are. It seems odd that the
latest date in the copyright date is 2003 when tools are
typically updated several times a year.

Cheers,
Jim

Hi,
I'm trying to simulate this in Cadence:
http://www.csee.umbc.edu/help/VHDL/samples/bmul32.vhdl

I don't have any problems with that,I can compile the files using
"ncvhdl -v93". I can also import the files in Synopsis and get gate
level as expected.

However, when I try to compile
http://www.csee.umbc.edu/help/VHDL/samples/bmul32_test.vhdl
I get this error.
ncvhdl: 05.10-p004: (c) 1995-2003 Cadence Design Systems, Inc.
ncvhdl_p: *internal* (expecting FUNCTION of PROCEDURE).
Please contact Cadence Design Systems about this problem and provide
enough information to help us reproduce is it.

I'm really stuck on this. Any help would be much appreciated.
Click to expand...

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
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