telling design compiler/vision to use SRAM to synthesize FIF

i have some verilog code for a synthesizable FIFO. i've declared a
register file. during synthesis with synopsys's design vision (design
compiler) is there any way i can provide hints to the synthesis tool
that it should use SRAM to implement the register file rather than
ordinary registers? what would be the directives for this?

thanks for any help.
pallav

 

[Berty]

Keep in mind when replacing FF with Memory there few timing aspect you
need to consider such as FF timing are "better" meaning for example
compare Clock to out of FF to Addr/clk to Data of the Memory and you
will see big difference as well as while this can be resolve with the
right logic generally speaking the "pure" memory generate the data one
clock later compare to FF.

Have fun.