techfile usage

Hi,
I am a newbie to layout design.

I have ami06 micron tech file .I want to draw the layout of an
inverter which has PMOS 31.5/1 and NMOS 25/1(1 micron tech).

I want to know how to use ami06 micron tech file to create the 1
micron inverter.what are the appropriate changes in layout editor and
other files that I have to make?

I changed the following display options of layout editor as

1.minor spacing = 0.5
2.major spacing = 1
3.xsnap spacing = 0.25
4.ysnap spacing = 0.25

and drawn the layout of nmos and done drc ,it displayed the following
error # errors Violated Rules
22 (SCMOS Rule 6.1) active contact size, exactly: 0.60 x 0.60 um
1 (DBM Rule 1.1) Active must be inside select
22 (SCMOS Rule 7.3) metal1 enclosure of contact: 0.30 um
88(SCMOS Inst) Edge not on grid


kindly help me to get rid of this

thanks a lot,
P selvakumar

 

[Bernd Fischer]

The layout display options you described have nothing to do
with the technology file at all, except that snap spacing should be
a multiplier of the manufacturing grid defined in the techfile.

The technology file has nothing to do with your drc errors, these come
form the drc command rule file, in your case could be 'divaDRC.rul'.

To explain this in detail would blast this posting.

My suggestion to you,
get the right required technology data form your foundry or
draw your cells with respect to the technology data you have.


Bernd


selvakumar_in@hotmail.com wrote:

Hi,
I am a newbie to layout design.

I have ami06 micron tech file .I want to draw the layout of an
inverter which has PMOS 31.5/1 and NMOS 25/1(1 micron tech).

I want to know how to use ami06 micron tech file to create the 1
micron inverter.what are the appropriate changes in layout editor and
other files that I have to make?

I changed the following display options of layout editor as

1.minor spacing = 0.5
2.major spacing = 1
3.xsnap spacing = 0.25
4.ysnap spacing = 0.25

and drawn the layout of nmos and done drc ,it displayed the following
error # errors Violated Rules
22 (SCMOS Rule 6.1) active contact size, exactly: 0.60 x 0.60 um
1 (DBM Rule 1.1) Active must be inside select
22 (SCMOS Rule 7.3) metal1 enclosure of contact: 0.30 um
88(SCMOS Inst) Edge not on grid


kindly help me to get rid of this

thanks a lot,
P selvakumar

 

[John Gianni]

My suggestion to you, get the right required technology data from your
foundry or draw your cells with respect to the technology data you have.

1. BTW, Cadence is shipping (soon) the new DRD (Design Rule Driven)
enhancement to the Virtuoso family of tools.

My flow team was asked to test DRD with a variety of real-world techfiles
on a variety of OpenAccess designs. It works well with most techfiles
in that it shows a variety of markers when you violate a selected set
of rules as defined in the techfile (yes, in the techfile).

We've seen some issues with complex techfiles (e.g., TSMC13LV as compared
to TSMC18RF or the Cadence GPDK18); all of which are being worked on.

2. Later DRD enhancements, I'm told, will improve the GUI & user interface,
and may (I understand) utilize the separate DRC rule decks (you can
get more complete info & a demo from your local Cadence sales team).

3. IMHO, with PCells, Design-Rule-Driven layout, & VirtuosoXL Gen-From-Source,
you should have a much easier time creating DRC-correct layout, even for
newbies.

--
All my USENET posts are personal opinion; none are company statements!