TCL Query on compilation for Verilog Files

[RSGUPTA]

I have 3 directories:
rtl/rtl.v
bench/rtl_bench.v
run/compile.tcl

This is my compile.tcl file
********************* Start of file *******************
set library_file_list {
design_library {../rtl/rtl.v}
test_library {../sim/rtl_bench.v}
}
set top_level test_library.rtl
set wave_patterns {
/*
}
proc r {} {uplevel #0 source pll_compile.tcl}
proc rr {} {global last_compile_time
set last_compile_time 0
r }
proc q {} {quit -force }
# Compile out of date files
set time_now [clock seconds]
if [catch {set last_compile_time}] {
set last_compile_time 0
}
foreach {library file_list} $library_file_list {
vlib $library
vmap work $library
foreach file $file_list {
if { $last_compile_time < [file mtime $file] } {
if [regexp {.vhdl?$} $file] {
vcom -93 $file
} else {
vlog $file
}
set last_compile_time 0
}
}
}
set last_compile_time $time_now

# Load the simulation
eval vsim $top_level

# Run the simulation
run -all
puts {
Script commands are:

r = Recompile changed and dependent files
rr = Recompile everything
q = Quit without confirmation
}

************ EOF ******************

I get the following error:

# QuestaSim vlog 6.4b Compiler
# -- Compiling module RTL
#
# Top level modules:
# RTL
# QuestaSim vlog 6.4b Compiler
# -- Compiling module rtl_sim
#
# Top level modules:
# rtl_sim
# vsim test_library.rtl_sim
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: ../sim/rtl_bench.v(74): Module 'RTL' is not defined.
# Optimization failed
# Error loading design

Where Have i have gone in not defining RTL in my script.??

 

On Feb 20, 12:37 am, RSGUPTA <rsgupta.gu...@gmail.com> wrote:

I have 3 directories:
rtl/rtl.v
bench/rtl_bench.v
run/compile.tcl

This is my compile.tcl file
********************* Start of file *******************
set library_file_list {
                           design_library {../rtl/rtl.v}
                           test_library   {.../sim/rtl_bench.v}}

[snip much]

Hmmm, that script looks awfully familiar. I know precisely
which of my colleagues to blame

# Top level modules:
#       rtl_sim
# vsim test_library.rtl_sim
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: ../sim/rtl_bench.v(74): Module 'RTL' is not defined.
# Optimization failed
# Error loading design

Where Have i have gone in not defining RTL in my script.??

Unlike VHDL, Verilog does not directly allow you to
specify the library in which an instanced module can
be found. "Your" script compiles the testbench and
the DUT into two different libraries. It then loads
the testbench (using vsim libname.modulename) and
ModelSim then does not know which library to scan
to find the compiled DUT.

It's easy to fix. Just add a suitable -L option
to the vsim command:

vsim -L design_library $top_level

Now VSIM knows that it should scan "design_library"
to look for any modules that it cannot otherwise find.
Since your module "RTL" is there, that should fix it.

There are many other ways to achieve the same effect;
for example, a `uselib directive in the testbench,
or (shudder) a Verilog configuration. The -L option
is by far the simplest.
--
Jonathan Bromley