tasks and #-delay

[Ralf Hildebrandt]

Hi!

I am facing the problem of modeling a task with a delay (e.g. #1000
and some signal assignments in it. (The purpose is pure testbench
behavior.) The behavior I get is not as expected. Signals seem to be
updated only at the end of the task.

A minimal example is attached to the posting in <task_define.v>. In all
examples 2 signals are are sequentially set using delay statements
(#1000. 2 tasks are included in this example - one using blocking- the
other using non-blocking signal assignments. Both have different and
unwanted behavior.

To make clear, what I really want to have, an example using a macro
(`define) is included in <task_define.v> too. Using the macro I get the
behavior I want to have. But my question is: What I am doing wrong using
tasks for this purpose?

Furthermore I attached <procedure.vhd>. I apologize for posting VHDL
code in this Verilog group, but the problem arises while translating
code from VHDL to Verilog. The VHDL code has the same behavior as the
Verilog macro and this is what I want to have.

Tasks in general can handle sequential statements using e.g.
"@posedge(clk)". (See the examples in
<http://www.asic-world.com/verilog/task_func1.html>.) But what about
#-delays?

Thanks in advance
Ralf

 

[Gabor]

Ralf Hildebrandt wrote:

Hi!

I am facing the problem of modeling a task with a delay (e.g. #1000
and some signal assignments in it. (The purpose is pure testbench
behavior.) The behavior I get is not as expected. Signals seem to be
updated only at the end of the task.

A minimal example is attached to the posting in <task_define.v>. In all
examples 2 signals are are sequentially set using delay statements
(#1000. 2 tasks are included in this example - one using blocking- the
other using non-blocking signal assignments. Both have different and
unwanted behavior.

To make clear, what I really want to have, an example using a macro
(`define) is included in <task_define.v> too. Using the macro I get the
behavior I want to have. But my question is: What I am doing wrong using
tasks for this purpose?

Furthermore I attached <procedure.vhd>. I apologize for posting VHDL
code in this Verilog group, but the problem arises while translating
code from VHDL to Verilog. The VHDL code has the same behavior as the
Verilog macro and this is what I want to have.

Tasks in general can handle sequential statements using e.g.
"@posedge(clk)". (See the examples in
http://www.asic-world.com/verilog/task_func1.html>.) But what about
#-delays?

Thanks in advance
Ralf

A task only updates its outputs (ports) when it completes. If you
want to use a task to create multiple events, then you need to use
named signals outside the scope of the task and its ports. If you need
to do the same task with multiple signals, then probably a macro will
be better. In your task, you are attempting to write to ports a
and b at different times. Inside the scope of the task (you can see
this in a simulation) task signals a and b will actually change
when you expected. However the signals mapped to the ports at the
higher level only get the final values of a and b when the task
completes. In the case of non-blocking assignments, the task
scope variables could actually change after the task completes,
and therefore the testbench scope signals won't ever be assigned
the final values.

-- Gabor

 

[Ralf Hildebrandt]

Hi Gabor!

A task only updates its outputs (ports) when it completes.

I was guessing that this does actually happen, but I was not sure about
it. Thank you for clarification.

If you
want to use a task to create multiple events, then you need to use
named signals outside the scope of the task and its ports.

Yes - global signals is a suitable option I have used before for solving
a similar problem when converting a procedure into a task.

For now I will use the solution with a macro, which seems to correspond
to a VHDL procedure quite well.

Thanks a lot.
Ralf

 

[Marcus Harnisch]

Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de> writes:

A task only updates its outputs (ports) when it completes.

I was guessing that this does actually happen, but I was not sure
about it. Thank you for clarification.

If your tool supports SystemVerilog, you may also use ref-ports, which
pass signals by reference rather than by value.

Kind regards
Marcus
--
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