Taskes of Classes in simvision

T

terabits

Guest
Hi

How can i see the taks with in classes using simvision ?
do i need to add anything to recordvars () ?

rgds
 
On Feb 9, 4:15 am, "terabits" <tera.b...@gmail.com> wrote:
Hi

How can i see the taks with in classes using simvision ?
do i need to add anything to recordvars () ?

rgds
I don't use IUS, but going by other simulators, SV class dumping to
waveform is not something as easy as that of modules, hence this may
be not yet implemented feature. IMHO in many cases one can do without
it. As we speak I'm writing a paper on Advanced Debugging for SV
testbenches for SNUG India 2007. That talks about special approaches
for testbenches. Some key points:

1. It really helps if the environment is layered - be it VMM or AVM
etc. I don't know much about uRM except its name, hope it has similar
layered approach.
2. If #1 is true, then the "task in waveform" is required only for
"command transactor" or BFM layer. And there we do have a virtual
interface, simply add few extra debug signals to that interface and
update the class members to that interface. This approach is detailed
in our 2006 SJ SNUG paper as well.

3. Even for any class this approach #2 works as a workaround.
4. For higher level models, breakpoints, transaction tracking etc. is
important. We are looking at Verdi, command line debugger etc. for
this.

Regards
Ajeetha, CVC
www.noveldv.com
 
Hi Ajeetha

Thank you for the response, will look at the work around and see how
it works for us,
is the 2006 papaer is by you, i tried to search snug but in vain,
could you pls send the link

rgds
Hi

How can i see the taks with in classes using simvision ?
do i need to add anything to recordvars () ?

rgds

I don't use IUS, but going by other simulators, SV class dumping to
waveform is not something as easy as that of modules, hence this may
be not yet implemented feature. IMHO in many cases one can do without
it. As we speak I'm writing a paper on Advanced Debugging for SV
testbenches for SNUG India 2007. That talks about special approaches
for testbenches. Some key points:

1. It really helps if the environment is layered - be it VMM or AVM
etc. I don't know much about uRM except its name, hope it has similar
layered approach.
2. If #1 is true, then the "task in waveform" is required only for
"command transactor" or BFM layer. And there we do have a virtual
interface, simply add few extra debug signals to that interface and
update the class members to that interface. This approach is detailed
in our 2006 SJ SNUG paper as well.

3. Even for any class this approach #2 works as a workaround.
4. For higher level models, breakpoints, transaction tracking etc. is
important. We are looking at Verdi, command line debugger etc. for
this.

Regards
Ajeetha, CVCwww.noveldv.com
 
On Feb 9, 9:51 pm, "terabits" <tera.b...@gmail.com> wrote:
Hi Ajeetha

Thank you for the response, will look at the work around and see how
it works for us,
is the 2006 papaer is by you, i tried to search snug but in vain,
could you pls send the link
Yes, it is titled as "VMMing a SystemVerilog testbench" BTW, I'm not
100% sure if this debug interface made to that paper or not, you may
see verificationguild link below for the same:

http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=1138&highlight=debugif


HTH
Ajeetha, CVC
www.noveldv.com
 
On Feb 9, 9:31 am, "Ajeetha (www.noveldv.com)" <ajee...@gmail.com>
wrote:
On Feb 9, 9:51 pm, "terabits" <tera.b...@gmail.com> wrote:

Hi Ajeetha
Thanks ajeetha..
will hv a look and get back

rgds


Thank you for the response, will look at the work around and see how
it works for us,
is the 2006 papaer is by you, i tried to search snug but in vain,
could you pls send the link

Yes, it is titled as "VMMing a SystemVerilog testbench" BTW, I'm not
100% sure if this debug interface made to that paper or not, you may
see verificationguild link below for the same:

http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t...

HTH
Ajeetha, CVCwww.noveldv.com
 

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