task

[rik]

Hi guys

I have an issue here.
Here is a testbench

parameter data1 = 4'b0010;

@(negedge tclk)
scan_ir(data1);
............


task scan_ir;
input [3:0] tdi_data;
integer k;
integer l;
parameter tms_value = 9'b0110_0_0110;

begin
for (k=0 ; k<9 ; k=k+1)
begin
tms = tms_value[k];
if (k==4)
begin
for (l=0; l<4; l=l+1)
begin
@(negedge tclk)
tdi_in= tdi_data[l];
if (y==3)
tms = 1;
end
end
@(negedge tclk);
end
end

endtask

I need to pass the value data1 to the task, where tdi_in is feed to the
value of tdi_data which inturn is data1. But I think there is a bug in,

tdi_in = tdi_data[l]
and is not getting executed as desired.

Can I pass in value like this. If yes how can I assign bit by bit
values to tdi_in with the value of data1, using task/functions.

 

[Jonathan Bromley]

On 18 Oct 2006 15:56:29 -0700, "rik" <ritwikbiswas@gmail.com> wrote:

Here is a testbench
[...]
...........
task scan_ir;
input [3:0] tdi_data;
integer k;
integer l;
parameter tms_value = 9'b0110_0_0110;

begin
[...]
tdi_in= tdi_data[l];
if (y==3)
tms = 1;
end
end
@(negedge tclk);

I need to pass the value data1 to the task, where tdi_in is feed to the
value of tdi_data which inturn is data1. But I think there is a bug in,

tdi_in = tdi_data[l]
and is not getting executed as desired.

What do you mean, "is not getting executed" ? If, as I assume,
tdi_in, tms, y and tclk are all things that are declared in the
task's enclosing module, then your code looks OK to me.
What actually happens, and why do you think it is wrong?

Can I pass in value like this.
Yes; that's what task input arguments are for.

What you *cannot* do is to wait for, or create
waveforms on, arguments of a task. Input arguments
are copied in when the task is called, and output
arguments are copied back when the task exits.

(Note to all you smart folk out there: yes, I know
that you *can* do that in SystemVerilog using
ref arguments...)
--
Jonathan Bromley, Consultant

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