task with real input

H

Holger Schmidt

Guest
Hi,

is it valid Verilog syntax (Verilog 2001) to have a task like this:

task in2out;
input in;
output out;
input real delay;
begin
#(delay) out = in;
end
endtask

The special thing is "real" type input. According to the IEEE Std.
1364-2001 an input can have a task_port_type which can be real (amongst
others). However, my Verilog compiler (Cadence ncvlog 5.7) complains
that the "real" is not an identifier which would be expected at that
position. It also says something about section 13.3.2 and 3.2.1 of the
LRM (don't know which version). But that sections do not seem to be
related. Any ideas?

Thanks,
Holger
 
On 15 Sep 2006 05:13:07 -0700, "Holger Schmidt" <schmidth@zmd.de>
wrote:

Hi,

is it valid Verilog syntax (Verilog 2001) to have a task like this:

task in2out;
input in;
output out;
input real delay;
begin
#(delay) out = in;
end
endtask

The special thing is "real" type input. According to the IEEE Std.
1364-2001 an input can have a task_port_type which can be real (amongst
others). However, my Verilog compiler (Cadence ncvlog 5.7) complains
that the "real" is not an identifier which would be expected at that
position.
Click to expand...
I think it's right. The problem is that you're conflating the "input"
specification with the type definition. That's OK in an ANSI-style
argument list, but not at that point in your code. Try one of the
following:

// Verilog-2001 version, doesn't work in V-95
task in2out (input in, output out, input real delay);
begin
...

// Verilog-95 version, also OK in V-2001
task in2out;
input in;
output out;
input delay;
real delay;
begin
...

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hi,
It perfectly worked in my simulator. I am using a vcs simulator.
(2005.09) edition.
it didnt give any error or warning.
i verified the code also with some test inputs .I am writing the code
with which i verified below:
module task_st;
reg in;
reg delay;
reg out;

initial begin
delay=1'b1;in=1'b1;
#10 delay=1'b0;in=1'b0;
#30 $finish;
end
always @(in,delay)
in2out(in,out,delay);


task in2out;
input in;
output out;
input real delay;
begin
#(delay) out = in;
end
endtask

endmodule
Holger Schmidt wrote:
Hi,

is it valid Verilog syntax (Verilog 2001) to have a task like this:

task in2out;
input in;
output out;
input real delay;
begin
#(delay) out = in;
end
endtask

The special thing is "real" type input. According to the IEEE Std.
1364-2001 an input can have a task_port_type which can be real (amongst
others). However, my Verilog compiler (Cadence ncvlog 5.7) complains
that the "real" is not an identifier which would be expected at that
position. It also says something about section 13.3.2 and 3.2.1 of the
LRM (don't know which version). But that sections do not seem to be
related. Any ideas?

Thanks,
Holger
Click to expand...
 
Jonathan Bromley wrote:
On 15 Sep 2006 05:13:07 -0700, "Holger Schmidt" <schmidth@zmd.de
wrote:

is it valid Verilog syntax (Verilog 2001) to have a task like this:

task in2out;
input in;
output out;
input real delay;
begin ...
endtask

I think it's right. The problem is that you're conflating the "input"
specification with the type definition. That's OK in an ANSI-style
argument list, but not at that point in your code. Try one of the
following:

// Verilog-2001 version, doesn't work in V-95
task in2out (input in, output out, input real delay);
begin
Click to expand...
I tried that, and a few other variants, but with the same error.

// Verilog-95 version, also OK in V-2001
task in2out;
input in;
output out;
input delay;
real delay;
begin
Click to expand...
That does the trick.

BTW, I used "The Verilog Golden Reference Guide" (v 2.0) from a company
called Doulos as reference. In that guide "TaskPort" expands to "Port
[PortType] Name,..." and "PortType" to "{one of} integer time real
realtime". It's not underlined, so I assumed it would be V-95 Syntax.
According to that, "input real delay" would be valid.

Thanks,
Holger
 
Holger Schmidt wrote:

It's not underlined, so I assumed it would be V-95 Syntax.
According to that, "input real delay" would be valid.
Click to expand...
It is not valid Verilog-1995 syntax. You need separate port and
variable declarations for that. But it is valid Verilog-2001 syntax.

Verilog-2001 allows the so-called "ANSI-C-style" port declarations. It
also allows using the same kind of combined port and variable
declarations without putting them in the port list.

It appears that NC-Verilog is not supporting reals in either
ANSI-C-style port lists or combined port/variable declarations for
tasks. I suspect that this is because reals are not allowed in module
port declarations, and task port lists are being parsed the same way.
I will file a bug report on this.
 
On 15 Sep 2006 07:34:08 -0700, "Holger Schmidt"
<schmidth@zmd.de> wrote:

BTW, I used "The Verilog Golden Reference Guide" (v 2.0) from a company
called Doulos as reference. In that guide "TaskPort" expands to "Port
[PortType] Name,..." and "PortType" to "{one of} integer time real
realtime". It's not underlined, so I assumed it would be V-95 Syntax.
According to that, "input real delay" would be valid.
Click to expand...
It's always good to get feedback on our Golden Reference Guides
so that we can keep them as useful as possible.

On the same page, the top line of syntax clearly shows the
"(TaskPort)" argument-list syntax as being optional in
Verilog-2001 - it's underlined there. Consequently it
didn't seem appropriate to clutter the page by underlining
all the syntax of TaskPort elsewhere. However, you
are right in that the optional [PortType] in the
expansion of TaskPort should be underlined. I've
raised an erratum for that. Thanks for spotting it.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
"Holger Schmidt" <schmidth@zmd.de> a écrit dans le message de news:
1158322387.469176.66920@k70g2000cwa.googlegroups.com...
Hi,

is it valid Verilog syntax (Verilog 2001) to have a task like this:

task in2out;
input in;
output out;
input real delay;
begin
#(delay) out = in;
end
endtask

The special thing is "real" type input. According to the IEEE Std.
1364-2001 an input can have a task_port_type which can be real (amongst
others). However, my Verilog compiler (Cadence ncvlog 5.7) complains
that the "real" is not an identifier which would be expected at that
position. It also says something about section 13.3.2 and 3.2.1 of the
LRM (don't know which version). But that sections do not seem to be
related. Any ideas?

Thanks,
Holger
Click to expand...
This compile and simulate correctly with ModelSim 6.1e in Verilog 2001
compilation mode:

module in2outmod(in,out);

input in;
output out;
reg out;

initial in2out(in,out,3.2);


task in2out;
input in;
output out;
input real delay;
begin
#(delay) out = in;
end
endtask
endmodule


Serge
 
Jonathan Bromley wrote:
On 15 Sep 2006 07:34:08 -0700, "Holger Schmidt" wrote:

BTW, I used "The Verilog Golden Reference Guide" (v 2.0) from a company
called Doulos as reference. In that guide "TaskPort" expands to "Port
[PortType] Name,..." and "PortType" to "{one of} integer time real
realtime". It's not underlined, so I assumed it would be V-95 Syntax.
According to that, "input real delay" would be valid.

It's always good to get feedback on our Golden Reference Guides
so that we can keep them as useful as possible.

On the same page, the top line of syntax clearly shows the
"(TaskPort)" argument-list syntax as being optional in
Verilog-2001 - it's underlined there. Consequently it
didn't seem appropriate to clutter the page by underlining
all the syntax of TaskPort elsewhere.
Click to expand...
It's true that TaskPorts in the argument list is underlined (indicating
Verilog 2001 syntax). But TaskPort is also "{one of}" "Declaration",
which is an element of "Declarations...", which comes right after the
Verilog 2001 style argument list (in the next line). None of them is
underlined.

Anyway, my original question was: Is "input real delay;" valid Verilog
2001 syntax for a task declaration? And both, the IEEE Verilog 2001
standard and the golden reference guide, define a task in a way that
make it look right. At least I read it that way.

In the standard a "task_declaration" can have a "task_item_declaration"
which can be "tf_input_declaration" which can be "input task_port_type
list_of_port_identifiers" and "task_port_type" can be "real" (Syntax
10-1: Syntax for task declaration).

Holger
 
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